Abstract: A related art imaging device is accompanied by the problem that it must perform read processing on pixel data generated within pixel units for every row, and an SN ratio of the pixel data is not capable of being enhanced sufficiently. According to one embodiment, an imaging device has common floating diffusion wirings and floating diffusion switches which switch whether or not to couple floating diffusions of a plurality of pixel units arranged in a column direction, and combines pixel data generated by the pixel units in the floating diffusions coupled within the pixel units.

Abstract: A related art imaging device is accompanied by the problem that it must perform read processing on pixel data generated within pixel units for every row, and an SN ratio of the pixel data is not capable of being enhanced sufficiently. According to one embodiment, an imaging device has common floating diffusion wirings and floating diffusion switches which switch whether or not to couple floating diffusions of a plurality of pixel units arranged in a column direction, and combines pixel data generated by the pixel units in the floating diffusions coupled within the pixel units.

Abstract: Image sensor devices of related art have a problem that an auto-focus accuracy deteriorates due to crosstalk of electrons between a plurality of photodiodes formed below one microlens. According to one embodiment, at least some of a plurality of pixels in an image sensor device include: first and second photoelectric conversion elements (PD_L, PD_R) that are formed on a semiconductor substrate below one microlens (45); and a potential barrier (34) that inhibits transfer of electric charges between at least a part of a lower region of the first photoelectric conversion element (PD_L) and at least a part of a lower region of the second photoelectric conversion element (PD_R) in a depth direction of the semiconductor substrate.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A resistance dividing circuit having the same voltage-dividing ratio as that of a voltage dividing circuit provided in a voltage-dividing voltage down-converting circuit divides a reference voltage employed in a direct feedback voltage down-converting circuit. The divided voltage is employed as the reference voltage for the voltage-dividing voltage down-converting circuit. A comparator cancels out temperature dependency of the resistance dividing circuit and the voltage dividing circuit by differential amplification, so that internal power supply voltages are identical in temperature dependency to each other. Thus, the internal power supply voltages generated by the direct feedback voltage down-converting circuit and the voltage-dividing voltage down-converting circuit have no difference in temperature dependency from each other.

Abstract: An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

Abstract: A memory controller is configured with a PLD, and includes an input pin for receiving an input of a control signal from the outside of a memory module, and input pin terminals for receiving inputs of electric signals. The memory controller controls the operation of a plurality of memory units in response to a control signal that has been passed through a filter circuit capable of adjusting cutoff frequency depending on the electric signals. Thus, noise is removed without modifying the design of the filter circuit depending on the system in which the memory module is incorporated.

Abstract: The DRAM includes a power supply switching circuit which provides a word line select circuit with a power supply potential when a test signal is activated. The potential of a main word line becomes an H level equal to the power supply potential when a word line is not selected. Thus, when a sub-decode signal attains an H level equal to a boosted potential, not only an N channel MOS transistor but also a P channel MOS transistor turn on in a word line driver, and a leakage current running through the word line driver comes to flow. Accordingly, large stress is imposed on the P channel MOS transistor.

Abstract: A memory chip includes a plurality of pins. The plurality of pins are divided into two rows for arrangement on the opposite sides of the memory chip. All data I/O pins are arranged on one side surface (in the same row) of a package. In the case of forming a memory module, each chip is arranged such that the data I/O pins may be nearest to a center line of a module substrate parallel to a connect pin group. Thereby, interconnections between the respective memory chips and the connect pins have substantially equal lengths.

Abstract: An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

Abstract: The DRAM includes a power supply switching circuit which provides a word line select circuit with a power supply potential when a test signal is activated. The potential of a main word line becomes an H level equal to the power supply potential when a word line is not selected. Thus, when a sub-decode signal attains an H level equal to a boosted potential, not only an N channel MOS transistor but also a P channel MOS transistor turn on in a word line driver, and a leakage current running through the word line driver comes to flow. Accordingly, large stress is imposed on the P channel MOS transistor.

Abstract: A memory controller is configured with a PLD, and includes an input pin for receiving an input of a control signal from the outside of a memory module, and input pin terminals for receiving inputs of electric signals. The memory controller controls the operation of a plurality of memory units in response to a control signal that has been passed through a filter circuit capable of adjusting cutoff frequency depending on the electric signals. Thus, noise is removed without modifying the design of the filter circuit depending on the system in which the memory module is incorporated.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.

Abstract: A semiconductor integrated circuit disclosed herein are characterized in that: (a) each chip is reduced in size by having electrode pads formed in a plurality of rows, the small-size chip being used to form a small ordinary package; (b) frame wires inside the package are used to interconnect electrode pads and electrode bumps in different manners so that chips are furnished in common, whereby a small-size mirror package is formed; (c) frame wires on one side are arranged to pass alternately between contiguous electrode pads and/or between contiguous frame wires on the other side in order to further reduce common chips in size, whereby electrode pads are formed in a larger number of rows; (d) a substrate is sandwiched by the CSPs thus obtained so as to at least double packaging density; and (e) switches or fuses are provided in layered connection wires inside the chip so that after package fabrication, the manner of interconnecting the internal circuits of the chip and the electrode pads thereof may be changed