Abstract: A first-conductive-type doped layer is provided on a second-conductive-type well, and a gate electrode of a MOS transistor and the first-conductive-type doped layer are connected to each other via a plug for filling a contact hole and a metal interconnect of Cu. Furthermore, a second-conductive-type doped layer is provided on a first-conductive-type well, and a gate electrode of a MOS transistor and the second-conductive-type doped layer are connected to each other via a plug for filling a contact hole and a metal interconnect of Cu. Then, a first diode and a second diode are provided between the gate electrode and the second-conductive-type well and between the gate electrode and the first-conductive-type well, respectively. Thus, antenna damage generated in the gate electrodes of the MOS transistors is prevented.

Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Abstract: A defect inspection apparatus includes a sensor which optically senses a circuit pattern formed on a plate to be inspected to obtain scanned image data thereof while moving relatively to the plate, an AD converter which converts the scanned image data into digital form, a normal image data generator which generates normal image data expressed by use of multiple values based on CAD data relating to the circuit pattern, a reference data generator which filters the normal image data to generate reference data while selecting filter coefficients according to the moving direction of the plate to be inspected by use of a finite response filter having asymmetrical coefficients, and a comparator which compares the reference data with the scanned image data.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout memory unit which stores therein a predicted final layout configuration that has been predicted by the central processing unit by adding an optical proximity effect to the design layout configuration.

Abstract: In a semiconductor integrated circuit design method for simulating a delay of a logic circuit based on delay values which are calculated for each kind of a plurality of cells composing the logic circuit or for each signal path of the logic circuit and which are stored in a delay library, the simulation is performed to a block including at least one cell, and a delay value varying dependent on a layout direction of the cell included in the block is used as the delay value in the delay library. By this method, timing verification can be performed according to the layout direction of each cell layouted on a wafer, attaining precise margin of the design and improving yield of the semiconductor integrated circuit.

Abstract: PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell. Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased. As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells. Therefore, variations in delays of signals generated between the standard cells can be suppressed.

Abstract: A first relational expression representing a relationship among gate bias Vd, carrier mobility ?, electric effective channel length Leff and transconductance Gm, and a second relational expression representing a relationship among maximum-transconductance ratio Gmmax L=Lref/Gmmax L=Ltar between a target transistor and a reference transistor and electric effective channel lengths Leff and Lref of the respective transistors are used. Maximum transconductance Gmmax obtained when gate bias Vd is changed is determined and electric effective channel length Leff is estimated by substituting the value of maximum transconductance Gmmax in the second relational expression. The correlation between 1/Gmmax and Lgsem is strong enough to allow maximum transconductance Gmmax to be used in monitoring a process variation of a physical gate length.

Abstract: A pattern inspection apparatus determines a difference of the measured dislocation of respective alignment marks of an opaque pattern and a phase shifting pattern (measurement difference), in addition to a difference between the both alignment mark positions in design (design difference). A difference between the measurement difference and the design difference is set as a difference in alignment mark position between the opaque pattern and the phase shifting pattern in a reference pattern which is later used in inspection. In this manner, by correcting one pattern data with respect to the other pattern data in the reference pattern, the displacement generated in the both patterns can be reflected, and the reference pattern data regarding an image of a sample which is actually observed can be created.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A pattern inspection apparatus determines a difference of the measured dislocation of respective alignment marks of an opaque pattern and a phase shifting pattern (measurement difference), in addition to a difference between the both alignment mark positions in design (design difference). A difference between the measurement difference and the design difference is set as a difference in alignment mark position between the opaque pattern and the phase shifting pattern in a reference pattern which is later used in inspection. In this manner, by correcting one pattern data with respect to the other pattern data in the reference pattern, the displacement generated in the both patterns can be reflected, and the reference pattern data regarding an image of a sample which is actually observed can be created.

Abstract: It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4?) are selectively formed in a surface of a body region (16), and extension regions (5) and (5?) are extended from tip portions of the source-drain regions (4) and (4?) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4?) including the extension regions (5) and (5?) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6?) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5?) and a peripheral portion of the extension region (5).

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

Abstract: A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).

Abstract: A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.