Patents by Inventor Kyoko Ishii
Kyoko Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150276244Abstract: A ventilation member 1 includes: a tubular inner member 2 adapted to be fitted to an opening portion 50a and having a through hole 2a whose opening is not equipped with a waterproof gas-permeable membrane and which serves as a part of a ventilation path 4 between a space inside a housing 50 and a space outside the housing 50; and a tubular outer member 3 having a bottom, fitted around the outer periphery of the inner member 2, and covering the opening of the through hole 2a. The inner member 2 and the outer member 3 are each formed of a hydrophobic material having a contact angle with water of 80 degrees or more.Type: ApplicationFiled: October 22, 2013Publication date: October 1, 2015Inventors: Kyoko Ishii, Youzou Yano
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Publication number: 20150050464Abstract: Provided is a porous polytetrafluoroethylene (PTFE) membrane that satisfies the following expressions: 0.2?F?4.0; 0.2?R?1.0; and R??0.1F+0.5, for the Frazier number F [cm3/sec/cm2] and the water entry pressure R [MPa]. This porous PTFE membrane may be a single-layer membrane. This porous PTFE membrane has the properties suitable for use as a waterproof air-permeable membrane, and achieves a good balance between high water resistance and high air permeability.Type: ApplicationFiled: July 4, 2012Publication date: February 19, 2015Inventors: Kyoko Ishii, Seiji Aizawa
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Publication number: 20140227960Abstract: A ventilation member includes: a first metal body including a flat portion having a first through-hole formed therein; an air-permeable membrane having a first principal surface and a second principal surface and placed on the flat portion of the first metal body so that the first principal surface covers the first through-hole; a second metal body including a flat portion having formed therein a second through-hole separated from the first through-hole by the air-permeable membrane, the second metal body being placed on a second principal surface side of the air-permeable membrane so that passage of air is permitted between the first through-hole and the second through-hole through the air-permeable membrane; and a joint portion fixing the first metal body and the second metal body to each other. The air-permeable membrane has a portion located outwardly of an outer end of the flat portion of the first metal body and an outer end of the flat portion of the second metal body.Type: ApplicationFiled: February 5, 2014Publication date: August 14, 2014Applicant: Nitto Denko CorporationInventors: Kyoko Ishii, Youzou Yano, Kouji Furuuchi
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Publication number: 20140196840Abstract: Provided is a method including: a step A of extruding a mixture containing a polytetrafluoroethylene (PTFE) fine powder having a standard specific gravity (SSG) of 2.19 or less and a liquid lubricant into a sheet using a flat die so as to obtain a PTFE sheet; a step B of rolling the PTFE sheet by passing the sheet between a pair of rolls in a longitudinal direction of the sheet; a step C of stretching the rolled PTFE sheet in a transverse direction of the sheet; a step D of removing the liquid lubricant from the PTFE sheet; and a step E of stretching the PTFE sheet, from which the liquid lubricant has been removed, both in the longitudinal direction of the sheet and in the transverse direction of the sheet, for example, at an area stretch ratio of 150 to 700, so as to make the sheet porous. According to this production method, it is possible to increase the PF value of the porous PTFE membrane.Type: ApplicationFiled: July 4, 2012Publication date: July 17, 2014Applicant: NITTO DENKO CORPORATIONInventors: Kyoko Ishii, Seiji Aizawa
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Patent number: 8734677Abstract: A liquid-crystal coating fluid which comprises: an azo compound represented by the following general formula (1); and a solvent to dissolve the azo compound: wherein Q1 is an aryl group which may have any substituent group; Q2 is an arylene group which may have any substituent group; R is a hydrogen atom, an alkyl group having 1 to 3 carbon atoms, an acetyl group, a benzoyl group, or a phenyl group which may have any substituent group; and M is a counter ion.Type: GrantFiled: June 17, 2010Date of Patent: May 27, 2014Assignee: Nitto Denko CorporationInventors: Shoichi Matsuda, Kyoko Ishii, Tadayuki Kameyama
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Publication number: 20140137739Abstract: A ventilation member is configured to be attached to an opening portion of a housing, and includes: an inner member configured to be fitted to the opening portion and including a tubular portion having a through hole configured to serve as a part of a ventilation path between a space inside the housing and a space outside the housing; and an outer member mounted to the inner member and covering a water-proof gas-permeable membrane attached so as to close an opening of the through hole. The inner member and the outer member have an exposed surface subjected to liquid-repellent treatment.Type: ApplicationFiled: November 19, 2013Publication date: May 22, 2014Applicant: NITTO DENKO CORPORATIONInventors: Kyoko ISHII, Youzou YANO, Yoshiki IKEYAMA
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Patent number: 8308998Abstract: The polarizing film of the present invention contains the azo compound represented by the following general formula (I). In the general formula (I), Q represents a substituted or unsubstituted aryl group, X represents a cationic group, a nitro group, a cyano group, or a hydroxyl group, and M represents a counter ion.Type: GrantFiled: April 20, 2010Date of Patent: November 13, 2012Assignee: Nitto Denko CorporationInventors: Shoichi Matsuda, Kyoko Ishii, Sadahiro Nakanishi, Tadayuki Kameyama
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Publication number: 20120062829Abstract: A liquid-crystal coating fluid which comprises: an azo compound represented by the following general formula (1); and a solvent to dissolve the azo compound: wherein Q1 is an aryl group which may have any substituent group; Q2 is an arylene group which may have any substituent group; R is a hydrogen atom, an alkyl group having 1 to 3 carbon atoms, an acetyl group, a benzoyl group, or a phenyl group which may have any substituent group; and M is a counter ion.Type: ApplicationFiled: June 17, 2010Publication date: March 15, 2012Applicant: NITTO DENKO CORPORATIONInventors: Shoichi Matsuda, Kyoko Ishii, Tadayuki Kameyama
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Publication number: 20100288166Abstract: The polarizing film of the present invention contains the azo compound represented by the following general formula (I). In the general formula (I), Q represents a substituted or unsubstituted aryl group, X represents a cationic group, a nitro group, a cyano group, or a hydroxyl group, and M represents a counter ion.Type: ApplicationFiled: April 20, 2010Publication date: November 18, 2010Applicant: NITTO DENKO CORPORATIONInventors: Shoichi Matsuda, Kyoko Ishii, Sadahiro Nakanishi, Tadayuki Kameyama
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Publication number: 20100136196Abstract: Poly-?-glutamic acid or a salt thereof is made to be present at the same time as a taste-exhibiting substance formed from a potassium salt.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: AJINOMOTO CO., INCInventors: Shin Sato, Hideo Satokawa, Takeshi Iwasaki, Yasuyuki Tomiyama, Kyoko Ishii, Katsuya Seguro
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Patent number: 5683716Abstract: This invention relates to an encapsulated pharmaceutical dosage form comprising a practically insoluble compound or salt and an intracapsular fluid, and/or a surfactant and/or cellulose derivative. It provides for increased oral absorption as compared with the conventional system because, on release of capsule contents from the capsule shell, the practically insoluble compound or salt undergoes diminution in crystal size.Type: GrantFiled: January 2, 1996Date of Patent: November 4, 1997Assignee: Fujisawa Pharmaceutical Co., Ltd.Inventors: Takehisa Hata, Fumio Shimojo, Kazutake Kado, Kyoko Ishii, Seiji Sawai
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Patent number: 5506804Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: November 30, 1993Date of Patent: April 9, 1996Assignees: Hitachi, Ltd., VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5440521Abstract: A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat.Type: GrantFiled: August 19, 1993Date of Patent: August 8, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Manabu Tsunozaki, Kyoko Ishii, Koichi Nozaki, Hiroshi Yoshioka, Yoshihisa Koyama, Shinji Udo, Hidetomo Aoyagi, Sinichi Miyatake, Makoto Morino, Akihiko Hoshida
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Patent number: 5426616Abstract: A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.Type: GrantFiled: May 16, 1994Date of Patent: June 20, 1995Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Tetsu Udagawa, Kyoko Ishii, Manabu Tsunozaki, Kazuyoshi Oshima, Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Shin'ichi Ikenaga, Kiyoo Itoh
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Patent number: 5335203Abstract: A semiconductor memory device has a plurality of divided memory blocks, each of which has its X-system addresses assigned so that an equal number of word lines in a plurality of sets of memory mats and sense amplifiers may be selected. Each memory block is equipped with a plurality of internal voltage drop circuits for generating a supply voltage from the outside into the operating voltages of the sense amplifiers.Type: GrantFiled: February 12, 1992Date of Patent: August 2, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kyoko Ishii, Shinichi Miyatake, Tsutomu Takahashi, Shinji Udo, Hiroshi Yoshioka, Mitsuhiro Takano, Makoto Morino
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Patent number: 5276648Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: January 8, 1992Date of Patent: January 4, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 5150325Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.Type: GrantFiled: March 20, 1990Date of Patent: September 22, 1992Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorpInventors: Kazumasa Yanagisawa, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Atsushi Nozoe, Masayuki Nakamura, Tetsurou Matsumoto, Yoshitaka Kinoshita, Yoshiaki Ouchi, Hiromi Tsukada, Shoji Wada, Kazuo Mihashi, Yutaka Kobayashi, Goro Kitsukawa
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Patent number: 4807190Abstract: A dynamic RAM is provided in which an output voltage of a booster circuit for forming a word line selection timing signal is rendered greater than a power source potential and less than a predetermined potential by providing voltage limitation means, thereby preventing destruction of circuit elements receiving the output voltage.Type: GrantFiled: February 24, 1987Date of Patent: February 21, 1989Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Kyoko Ishii, Kazumasa Yanagisawa, Masaya Muranaka
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Patent number: 4211118Abstract: An ultrasonic fault detector for inspecting the welds of a welded pipe comprises a casing in which contact medium is contained, an arm movable in the casing, a movable member rotatably secured to the arc, probe heads mounted on the movable member, and a pump for feeding the contact medium to the operating surface of the probe heads. The movable member is constructed to be dividable into two or more parts.Type: GrantFiled: May 16, 1978Date of Patent: July 8, 1980Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Yoshishige Sakurai, Hiroshi Yamada, Kuniharu Uchida, Kanekichi Suzuki, Ryoichi Ishii, deceased, by Kyoko Ishii, administrator