Abstract: Provided is a silicone adsorption film that excels in both adsorption to a smooth surface and the suppression of remnants of glue on the smooth surface after detachment. The silicone adsorption film comprises a base material layer and a silicone adsorption layer laminated on the base material layer. The silicone adsorption layer is a cured product of a crosslinkable composition containing (a) a crosslinkable organopolysiloxane, (b) a crosslinking agent, (c) a non-reactive MQ resin and (d) a reactive MQ resin. The silicone adsorption film excels in both adsorption to a smooth surface and the suppression of remnants of glue on the smooth surface after detachment.

Abstract: A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal.

Abstract: A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal.

Abstract: A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.

Abstract: A microcomputer which is to be utilized in a condition of being built into an apparatus such as a vehicle ECU, includes a ROM having stored therein a program which is prepared by a user and a boot ROM which stores an initialization program for performing at least essential initialization processing which is required for all application programs that will be executed by the microcomputer. The need for the user to generate program contents relating to such initialization processing is thereby eliminated, while increased reliability of operation of the microcomputer is achieved. In addition, it is possible for user-specified initialization data to be read out from a user program and utilized in a part of the initialization processing of the initialization program.

Abstract: In an electronic control system, it is determined whether leading end identification information in a data verification space of a flash EEPROM of an electronic control unit is an expected value. When it is yes, it is then determined whether terminal identification information in the data verification space is the expected value. Then, when it is yes, it is determined whether the leading end identification information and the trailing end identification information are identical to each other. When it is yes, it is determined that data between the leading end identification information and the trailing end identification information is valid. Otherwise, it is determined that the data is invalid.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: Featured is a device for generating a 3-D model of a target object detects size, position, and direction of the target object in an input image. The device calculates the position of each vertex of a 3-D rough geometric model projected onto a 2-D plane in the detected size, position, and direction, as well as onto a 2-D plane in a predetermined size, position, and direction. The device also modifies the input image based on a correspondence relationship between the position of each vertex of the 3-D rough geometric model calculated by the first calculation means and the position of each vertex of the 3-D rough geometric model calculated by the second calculation means to generate a texture images and maps the texture image to the 3-D rough geometric model.

Abstract: An image processing device for generating a 3-D model image of a target object included in an input image, comprises a face image input means for inputting a face image; a 3-D model input means for inputting one or a plurality of 3-D models for each of a plurality of parts; a 3-D model selection means for selecting a 3-D model for an arbitrary part of the plurality of parts based on an instruction input by an operator; a face image mapping means for mapping the face image input via the face image input means to the 3-D model selected by the 3-D model selection means and for displaying the mapped 3-D model; and an image generation means for generating a 3-D still image using the 3-D model selected by the 3-D model selection means and the face image input by the face image input means.

Abstract: Where instruction data to enable a stop control is stored in an operation setting register that is provided in a peripheral module in an evaluation chip, a stop control circuit of the peripheral module stops the progress of an operation of a functional circuit until a CPU completes processing of a monitor program that is performed in response to a break interrupt request. None of the operation setting register, the stop control circuit, and an interface circuit are reset by a reset signal supplied from a circuit board as a target system. The CPU directly starts execution of a user program without starting the monitor program.

Abstract: A microcomputer which is to be utilized in a condition of being built into an apparatus such as a vehicle ECU, includes a ROM having stored therein a program which is prepared by a user and a boot ROM which stores an initialization program for performing at least essential initialization processing which is required for all application programs that will be executed by the microcomputer. The need for the user to generate program contents relating to such initialization processing is thereby eliminated, while increased reliability of operation of the microcomputer is achieved. In addition, it is possible for user-specified initialization data to be read out from a user program and utilized in a part of the initialization processing of the initialization program.

Abstract: A color image-forming method, comprising the steps of: using a transfer sheet comprising a foundation, a release layer and a colored ink layer stacked in this order on one side of the foundation wherein the release layer is capable of being fused or softened by heat at the time of a thermal transferring process and the colored ink layer is incapable of being softened by heat at the time of the thermal transferring process; and an image receiving body having at least a surface layer capable of being fused or softened by heat at the time of the thermal transferring process, superposing the colored ink layer of the transfer sheet onto the image receiving body and heating the transfer sheet/image receiving body from the transfer sheet side to form a color image on the image receiving body.

Abstract: To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section.