Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.

Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

Abstract: A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.

Abstract: In one embodiment, the boost circuit includes a boost unit configured to perform a charge pumping operation based on a control signal. A controller is configured to control the boost unit such that the boost unit performs a lesser charge pumping operation from an initial time when power is supplied to the boost circuit until a desired time than after the desired time.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: An image sensor includes first and second pixel circuits and an output node coupled to the first and second pixel circuits. A bias circuit provides a higher bias current at the output node during a sub-sampling mode of operation of the image sensor for improved image quality.

Abstract: A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in synchronization with a clock signal. The second state storage unit performs transition of a second state value in synchronization with a first state signal corresponding to the first state value. The first control signal generating unit generates a first control signal for determining a first state transition path based on a first division ratio control signal. The state update unit generates the update signal based on the first control signal and the first state signal. The output unit selectively output the first state signal or a second state signal corresponding to the second state value.

Abstract: A DC-DC converter includes a PWM modulator, a power switch and a filter. The PWM modulator positively feeds back a pulse width modulated signal of which a pulse width and a frequency are varied to generate an oscillated signal, amplifies a difference between a negatively fed-back direct current output signal and a reference signal to output a first signal, and compares the first signal with the oscillated signal to generate first and second switching signals. The power switch transfers an input signal to a first output node in response to the first and second switching signals, and generates the pulse width modulated signal, wherein the pulse width modulated signal is provided to the first output node. The filter generates a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node.

Abstract: A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in synchronization with a clock signal. The second state storage unit performs transition of a second state value in synchronization with a first state signal corresponding to the first state value. The first control signal generating unit generates a first control signal for determining a first state transition path based on a first division ratio control signal. The state update unit generates the update signal based on the first control signal and the first state signal. The output unit selectively output the first state signal or a second state signal corresponding to the second state value.

Abstract: An image sensor includes first and second pixel circuits and an output node coupled to the first and second pixel circuits. A bias circuit provides a higher bias current at the output node during a sub-sampling mode of operation of the image sensor for improved image quality.

Abstract: A DC-DC converter includes a PWM modulator, a power switch and a filter. The PWM modulator positively feeds back a pulse width modulated signal of which a pulse width and a frequency are varied to generate an oscillated signal, amplifies a difference between a negatively fed-back direct current output signal and a reference signal to output a first signal, and compares the first signal with the oscillated signal to generate first and second switching signals. The power switch transfers an input signal to a first output node in response to the first and second switching signals, and generates the pulse width modulated signal, wherein the pulse width modulated signal is provided to the first output node. The filter generates a direct current output voltage signal in response to the pulse width modulated signal, wherein the direct current output voltage signal is provided to a second output node.