Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

Abstract: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.

Abstract: A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure.

Abstract: In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Abstract: An absorbable multifilament draw-textured yarn having a bulky structure, and a manufacturing method and medical use thereof The absorbable multifilament draw-textured yarn is obtained by draw-texturing a multifilament made of an absorbable polymer and has bulkiness and a superior soft touch, which are the characteristics of draw-textured yarns. As a result of partially imparting a bulkiness of 150-1000% to the multifilament draw-textured yarn, it is possible to culture cells in the bulky structure, and the multifilament draw-textured yarn is suitable for cell delivery or drug delivery.

Abstract: Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate.

Abstract: An actuator using a piezoelectric element and a method of driving the same. The actuator includes at least one piezoelectric cell moving by displacement according to an input voltage, at least one piezoelectric sensor sensing the displacement of the at least one piezoelectric cell, an error detector detecting an error in the at least one piezoelectric sensor, and a feedback signal generator generating a feedback signal corresponding to the error, thereby performing micromirror driving and sensing.

Abstract: Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided.

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Abstract: An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.

Abstract: Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

Abstract: Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Abstract: A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench.

Abstract: A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.

Abstract: A method for deciding a network manager (NM) in a home network, including the steps of comparing a priority of a current NM and a priority of a new NM when the new NM is plugged-in a home network which is controlled by the current NM and deciding a NM having a higher priority as the NM of the home network between the current NM and the new NM, can smoothly control and manage the home network by deciding a NM having a higher priority as the NM for centralized-controlling the home network.