Abstract: A gallium nitride (GaN) power device includes a GaN substrate structure having a first surface and a second surface, a metallic layer coupled to the second surface of the GaN substrate structure, and an active region including an array of vertical fin-based field effect transistors (FinFETs) coupled to the GaN substrate structure. The GaN power device also includes an edge termination structure circumscribing the active region and a seal ring structure circumscribing the edge termination structure and comprising a seal ring metal pad operable to conduct charge from the edge termination structure to the metallic layer.

Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.

Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.

Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.

Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.

Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.

Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.

Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.

Abstract: In one embodiment, a power semiconductor device may include a semiconductor substrate, wherein the semiconductor substrate comprises an active device region and a junction termination region. The power semiconductor device may also include a polysilicon layer, disposed over the semiconductor substrate. The polysilicon layer may include an active device portion, disposed over the active device region, and defining at least one semiconductor device; and a junction termination portion, disposed over the junction termination region, the junction termination portion defining a ring structure.

Abstract: An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers.

Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

Abstract: A trench IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a novel waved contour so that it has thinner portions and thicker portions. When the IGBT is on, electrons flow from an N+ emitter, vertically through a channel along a trench sidewall, and to an N? type drift layer. Additional electrons flow through the channel but then pass under the trench, through the floating P well to the floating N+ well, and laterally through the floating N+ well. NPN transistors are located at thinner portions of the floating P type well. The NPN transistors inject electrons from the floating N+ type well down into the N? drift layer. The extra electron injection reduces VCE(SAT). The waved contour can be made without adding any masking step to an IGBT manufacturing process.

Abstract: A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P? type columns, a floating ring-shaped P? type column that surrounds the set of strip-shaped P? type columns, and a set of ring-shaped P? type columns that surrounds the floating ring-shaped P? type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P? type columns and each of the ring-shaped P? type columns. An oxide is disposed between the floating P? type column and the source metal such that the floating P? type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P? type column were to contact the source metal.

Abstract: An inverse diode die is “fast” (i.e., has a small peak reverse recovery current) due to the presence of a novel topside P+ type charge carrier extraction region and a lightly-doped bottomside transparent anode. During forward conduction, the number of charge carriers in the N? type drift region is reduced due to holes being continuously extracted by an electric field set up by the P+ type charge carrier extraction region. Electrons are extracted by the transparent anode. When the voltage across the device is then reversed, the magnitude of the peak reverse recovery current is reduced due to there being a smaller number of charge carriers that need to be removed before the diode can begin reverse blocking mode operation. Advantageously, the diode is fast without having to include lifetime killers or otherwise introduce recombination centers. The inverse diode therefore has a desirably small reverse leakage current.

Abstract: An AC-to-DC converter circuit includes DC-to-DC converter that in turn includes a secondary side circuit. The secondary side circuit includes a secondary winding, a pair of bipolar transistor-based self-driven synchronous rectifiers, a pair of current splitting inductors, and an output capacitor. Each of the synchronous rectifiers includes a bipolar transistor and a diode whose anode is coupled to the transistor collector and whose cathode is coupled to the transistor emitter. The current splitting inductors provide the necessary base current to the bipolar transistors at the appropriate times such that the bipolar transistors operate as synchronous rectifiers.

Abstract: An IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour with thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter and through a channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to one of the thinner portions of the floating P type well. The electrons then pass down from the thinner portions into the N? drift layer. Other electrons pass farther through the floating N+ well to subsequent, thinner electron injector portions of the floating P type well and then into the N? drift layer. The extra electron injection afforded by the waved floating well structure reduces VCE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.

Abstract: A trench N-channel field effect transistor has an active area and an edge area. A first pair of parallel-extending deep trenches extends parallel to a side edge of the die. A second pair of parallel-extending deep trenches extends perpendicularly to the side edge, toward the side edge, so that each trench of the second pair terminates into the inside deep trench of the first pair. An embedded field plate structure is embedded in these trenches. A plurality of floating P type well regions is disposed entirely between the second pair of deep trenches, between the active area and the inside deep trench of the first pair. Using this edge area structure, the breakdown voltage BVDSS of the overall device is increased because the breakdown voltage of the edge area is increased as compared to the same structure without the floating P type well regions.

Abstract: A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.

Abstract: A combination switch includes an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, and a saturable inductor. The diode and inductor are coupled in series between a collector and an emitter of the IGBT. The inductor is fashioned so that it will come out of saturation when a forward bias current flow through the diode falls below a saturation current level. When the diode current falls (for example, due to another combination switch of a phase leg turning on), the diode current initially falls at a high rate until the inductor current drops to the saturation current level. Thereafter, the diode current falls at a lower rate. The lower rate allows the diode current to have a soft landing to zero current, thereby eliminating or reducing voltage and/or current spikes that would otherwise occur. Multiple methods of implementing and manufacturing the saturable inductor are disclosed.

Abstract: A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.