Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

Abstract: A method of manufacturing an integrated circuit (IC) device includes exposing a partial region of a photoresist film formed on a main surface of a substrate to generate acid, and diffusing the acid in the partial region of the photoresist film. Diffusing the acid may include applying an electric field, in a direction perpendicular to a direction in which the main surface of the substrate extends, to the photoresist film using an electrode facing the substrate through an electric-field transmission layer filling between the photoresist film and the electrode. The electric-field transmission layer may include an ion-containing layer or a conductive polymer layer.

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

Abstract: A gas injection apparatus, which can sequentially supply a substrate with at least two kinds of source gases reacting with each other in a container, and thin film deposition equipment including the gas injection apparatus, are provided. The gas injection apparatus includes a base plate, a first gas supply region protruding from the base plate, a second gas supply region protruding from the base plate and adjacent the first gas supply region, and a trench defined by a sidewall of the first gas supply region and a sidewall of the second gas supply region. The sidewall of the first gas supply region and the sidewall of the second gas supply region face each other and extend in a radial direction on the base plate.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.

Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.