Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, peripheral circuits for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuits to perform a detrap operation between a program voltage apply operation and a program verify operation during the program operation, and the peripheral circuits apply a positive set voltage to a source line connected to the selected memory block during the detrap operation.

Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.

Abstract: An input/output sense amplifier is configured to amplify data inputted through a pair of local transmission lines in response to a sense amplifier enable signal and a test mode signal, output the data through a global transmission line, generate a control signal by sensing whether the data have been amplified, and halt amplification of the data in response to the control signal when amplification is completed.

Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.

Abstract: A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Abstract: An input/output sense amplifier is configured to amplify data inputted through a pair of local transmission lines in response to a sense amplifier enable signal and a test mode signal, output the data through a global transmission line, generate a control signal by sensing whether the data have been amplified, and halt amplification of the data in response to the control signal when amplification is completed.

Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.

Abstract: A semiconductor memory apparatus includes: a first sense amplification unit including first and second inverters configured to be driven to voltage levels of a power driving signal and a ground driving signal and forming a latch structure between a bit line and a bit line bar; and a second sense amplification unit including first and second transistors configured to be driven to the voltage level of the ground driving signal and forming a latch structure between the bit line and the bit line bar when an activated switching signal is applied, wherein a threshold voltage of the second sense amplification unit is set lower than that of the first sense amplification unit.

Abstract: A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.

Abstract: A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.

Abstract: Provided is a circuit and method of generating a boosted voltage while maintaining a constant difference between the boosted voltage and an array reference voltage when the array reference voltage is varied in a normal mode, a test mode, and a burn-in test mode of a semiconductor device. The boosted voltage generating circuit comprises a sensing signal generating circuit which generates a sensing signal, a pulse generating circuit which generates a driving signal in response to the sensing signal, and a pumping circuit which generates the boosted voltage in response to the driving signal to control a word line of a semiconductor device.

Abstract: A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Abstract: Provided is a semiconductor device that is insensitive to a change in a power supply voltage, inconsistencies in a manufacturing process, and a change in temperature and provides for a rapid read data operation. The semiconductor device includes a first read signal generator, a second read signal generator, and a voltage input/output sense amplifier. The first read signal generator generates a first read signal for sampling data in response to an enable signal of a column selection line. The second read signal generator generates a second read signal including a plurality of pulses during an enabling period of the first read signal in response to the first read signal. The voltage input/output sense amplifier receives a data value output from a memory cell, amplifies the data value in synchronization with the column selection line, and samples the data value in synchronization with enabling signals of the second read signal.

Abstract: A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.

Abstract: Provided is a semiconductor device that is insensitive to a change in a power supply voltage, inconsistencies in a manufacturing process, and a change in temperature and provides for a rapid read data operation. The semiconductor device includes a first read signal generator, a second read signal generator, and a voltage input/output sense amplifier. The first read signal generator generates a first read signal for sampling data in response to an enable signal of a column selection line. The second read signal generator generates a second read signal including a plurality of pulses during an enabling period of the first read signal in response to the first read signal. The voltage input/output sense amplifier receives a data value output from a memory cell, amplifies the data value in synchronization with the column selection line, and samples the data value in synchronization with enabling signals of the second read signal.

Abstract: A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

Abstract: A semiconductor memory device having a bit line sense amplifier connected to a bit line pair may include a precharge part to precharge first and second drive nodes of the bit line sense amplifier to an equal voltage level. The device may include a switching part operatively connecting the first and second precharge nodes to the first and second drive nodes in response to sense amplifier drive signals applied during a data non-access mode. To drive power in the bit line sense amplifier, the precharge voltage may be applied in a precharge state to precharge the first and second drive nodes to the equal voltage level, the device may shift from the precharge state to an operational state to cut off the applied precharge voltage, and driving voltages may be applied to the first and second drive nodes to power the bit line sense amplifier of the device.

Abstract: Provided is a circuit and method of generating a boosted voltage while maintaining a constant difference between the boosted voltage and an array reference voltage when the array reference voltage is varied in a normal mode, a test mode, and a burn-in test mode of a semiconductor device. The boosted voltage generating circuit comprises a sensing signal generating circuit which generates a sensing signal, a pulse generating circuit which generates a driving signal in response to the sensing signal, and a pumping circuit which generates the boosted voltage in response to the driving signal to control a word line of a semiconductor device.