Patents by Inventor Kyu-Hyun Bang

Kyu-Hyun Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor
    Patent number: 6919212
    Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 19, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hyun Oh, Kyu-Hyun Bang, In-Woo Jang, Jin-Yong Seong, Jin-Gu Kim, Song-Hee Park, Young-Ho Yang, Kye-Nam Lee, Suk-Kyoung Hong
  • Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor
    Publication number: 20040266032
    Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.
    Type: Application
    Filed: December 18, 2003
    Publication date: December 30, 2004
    Inventors: Sang-Hyun Oh, Kyu-Hyun Bang, In-Woo Jang, Jin-Yong Seong, Jin-Gu Kim, Song-Hee Park, Young-Ho Yang, Kye-Nam Lee, Suk-Kyoung Hong