Patents by Inventor Kyung A DO

Kyung A DO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120306008
    Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kyung Do KIM
  • Publication number: 20120289024
    Abstract: A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.
    Type: Application
    Filed: August 16, 2011
    Publication date: November 15, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kyung Do KIM
  • Publication number: 20120237582
    Abstract: Provided are a method of preparing a silica powder coated with an antibacterial agent and a topical dermatological composition including the silica powder, and more particularly, a method of preparing a silica powder coated with an antibacterial agent by forming a silica particle by inducing a reaction between silicon alkoxide and alcohol solvent in the presence of a catalyst and then forming an silver and metallic coating layer on the silica particle, and a method of preparing a topical dermatological composition including the silica powder. The silica powder coated with the antibacterial agent may have high antibacterial capability, and thus, topical dermatological products including the silica powder may be maintained for a long time without using a chemical antiseptic agent that may irritate the skin and cause an allergy in the human body. Even if a small amount of expensive silver (Ag) ion material is used, the silica powder has excellent antibacterial capability and stability.
    Type: Application
    Filed: December 11, 2009
    Publication date: September 20, 2012
    Applicant: ACT CO., LTD.
    Inventors: Youn-kyung Do, Yun-jeong Kim, Ji-hyun Son, Hyun-sang Lee, Jong-woo Cheon
  • Patent number: 8263460
    Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operational gate and a dummy gate. A height of a gate electrode layer (conductive material) of the dummy gate is formed to be lower than that of a gate electrode layer of the operational gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the dummy gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: September 11, 2012
    Assignee: Hynix Semiconductor Inc
    Inventor: Kyung Do Kim
  • Publication number: 20120180951
    Abstract: An automatic spacers mounting system is provided which comprises a horizontal arraying device; a vertical arraying device comprising a vertical arraying pallet and a reversing device; a mounting base which fixes the vertical arraying pallet and a panel; a vacuum absorbing device to absorb a plurality of spacers vertically arrayed in the vertical arraying pallet; a guiding and pressing device which guides a plurality of spacers from the vacuum absorbing device to the panel and a pressing plate that presses the plurality of spacers. A first loader allows the vacuum absorbing device to move from the vertical arraying pallet to above the panel, and a second loader allows the guiding and pressing device to move above the panel. A controller controls the vertical arraying device, the vacuum absorbing device, the guiding and pressing device, and the first and second loaders to mount the plurality of spacers on the panel.
    Type: Application
    Filed: November 7, 2011
    Publication date: July 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-do PARK, Jin-uk HONG, Kyu-ho KIM
  • Publication number: 20120175036
    Abstract: An automatic spacers mounting system includes a horizontal arraying pallet to hold spacers therein in a horizontal direction; a posture changing pallet and a shutter. The posture changing pallet and the shutter are coupled to the horizontal arraying pallet, such that the posture changing pallet faces the horizontal arraying pallet, and are rotated by 180 degrees with the horizontal arraying pallet. An inserting guide having a plurality of guiding holes is positioned above a panel having sprayed glue thereon is placed. The posture changing pallet and the shutter are disposed above the inserting guide, the plurality of spacers are inserted into the plurality of guiding holes, and a plurality of pressing pins of a pressing chuck are inserted in the guiding holes and press the spacers against the panel.
    Type: Application
    Filed: August 15, 2011
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-uk HONG, Kyung-do PARK, Kyu-ho KIM
  • Patent number: 8202781
    Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: June 19, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Publication number: 20120146121
    Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).
    Type: Application
    Filed: December 31, 2010
    Publication date: June 14, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kyung Do KIM
  • Patent number: 8143127
    Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8117792
    Abstract: Disclosed are a fixing structure of insulation panels and a prefabricated refrigerator with the same. The fixing structure of insulation panels includes a recess recessed on one surface of a first insulation panel having an insulation portion inside a casing, and a protrusion formed to be inserted into the recess, on one surface of a second insulation panel having an insulation portion inside a casing, wherein the insulation portions of nonmetal material are exposed to a bottom of the recess and a front end of the protrusion so as to shield a transmission path of heat flowed along a casing contact surface of the insulation panels, thereby improving insulation efficiency.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: February 21, 2012
    Assignee: LG Electronics Inc.
    Inventors: Young-Bae Kim, Kyung-Do Kim, Dong-Ju Jung
  • Publication number: 20110301303
    Abstract: The present invention relates to a process for preparing a water absorbent resin, particularly to a process for preparing a water absorbent resin which can resolve the uneven size of the fine pulverized gel-type resin and long pulverizing time those are the problems of prior process for preparing the water absorbent resin, by carrying out the pulverizing process of the gel-type resin divided into the coarse pulverizing process which is carried out with the internal cross-linking polymerization, and the fine pulverizing process. According to the preparation process, it is possible to mass-produce the water absorbent resin showing excellent absorption under pressure and low extractable content.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 8, 2011
    Applicant: LG CHEM, LTD.
    Inventors: Jun-Kyu KIM, Jong-Hyuk KWON, Young-Jae HUR, Yun-Kyung DO
  • Publication number: 20110263090
    Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
    Type: Application
    Filed: July 7, 2011
    Publication date: October 27, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Kyung Do KIM
  • Publication number: 20110248339
    Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.
    Type: Application
    Filed: July 29, 2010
    Publication date: October 13, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 7999313
    Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 7993723
    Abstract: A vacuum insulation panel and an insulation structure of a refrigerator applying the same are disclosed. The vacuum insulation panel comprises: a sealing cover (120) having an outermost layer exposed to the outside, a gas shielding layer stacked on the bottom surface of the outermost layer and formed of a thin metal sheet and a metal deposition film, and a heating-fusion bonding layer stacked on the bottom surface of the gas shielding layer and formed of an octane-base material; a core material (110) sealed by the sealing cover (120) in contact with the heating-fusion bonding layer, and provided with an extended insulation portion (130) some parts of which are extended between the bonding portions formed at the sealing cover (120); and a gas permeation preventing layer (125) formed on the sealing cover (120), so that can prevent an external air or moisture from penetrating into a vacuum insulation panel.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: August 9, 2011
    Assignee: LG Electronics Inc.
    Inventors: Dong-Ju Jung, Young-Bae Kim, Kyung-Do Kim, Sang-Eui Hong
  • Publication number: 20110165747
    Abstract: A method for manufacturing a semiconductor apparatus includes forming a contact pad layer over a substrate in an active region; patterning the contact pad layer and the substrate to form a first trench, the first trench defining a contact pad pattern; etching the substrate to form a second trench that extends vertically from the first trench; forming a gate insulating pattern over the substrate in the second trench; and forming a buried gate in the second trench.
    Type: Application
    Filed: July 20, 2010
    Publication date: July 7, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kyung Do KIM
  • Publication number: 20110048510
    Abstract: A sealant disposed between two substrates to be sealed, the sealant comprising: at least two layers disposed layered on top of each other between the two substrates, wherein the at least two layers comprise materials having different components and at least one layer selected from the at least two layers includes a thermoplastic glass frit. A dye-sensitized solar cell including the sealant, and a method of manufacturing a dye-sensitized solar cell are also provided.
    Type: Application
    Filed: March 31, 2010
    Publication date: March 3, 2011
    Applicant: SAMSUNG SDI CO., LTD.
    Inventors: Nam-Choul YANG, Ji-Won LEE, Won-Shik PARK, Kyung-Do PARK
  • Patent number: 7871887
    Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung Do Kim, Seung Joo Baek
  • Publication number: 20110008942
    Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.
    Type: Application
    Filed: September 22, 2010
    Publication date: January 13, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Kyung Do KIM
  • Publication number: 20100310887
    Abstract: Provided are a decoration panel and a home appliance with the decoration panel. The decoration panel includes a transparent green glass defining an outer appearance and a decoration film adhered to the green glass to realize a color and pattern seen through the green glass to the outside. The decoration film includes a print layer on which the color and pattern expressed to the outside are printed using a gravure printing process and a reflective layer in which a printing ink containing a white inorganic pigment for improving a color reflectance is printed using the gravure printing process to conceal a green color of the green glass, the reflective layer being disposed on a back surface of the print layer. Thus, an outer appearance of the home appliance may be improved.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 9, 2010
    Applicant: LG ELECTRONICS INC.
    Inventors: Kyung Do KIM, Hyun Woo JUN, Min Ju SON, Seok Jae JEONG, Hyun Gi JUNG, Young Kyu KIM