Patents by Inventor Kyung-Hee Jang

Kyung-Hee Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983501
    Abstract: The present invention relates to an apparatus and method for automatically generating machine reading comprehension training data, and more particularly, to an apparatus and method for automatically generating and managing machine reading comprehension training data based on text semantic analysis. The apparatus for automatically generating machine reading comprehension training data according to the present invention includes a domain selection text collection unit configured to collect pieces of text data according to domains and subjects, a paragraph selection unit configured to select a paragraph using the pieces of collected text data and determine whether questions and correct answers are generatable, and a question and correct answer generation unit configured to generate questions and correct answers from the selected paragraph.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 14, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Jin Bae, Joon Ho Lim, Min Ho Kim, Hyun Kim, Hyun Ki Kim, Ji Hee Ryu, Kyung Man Bae, Hyung Jik Lee, Soo Jong Lim, Myung Gil Jang, Mi Ran Choi, Jeong Heo
  • Publication number: 20240145474
    Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.
    Type: Application
    Filed: May 9, 2023
    Publication date: May 2, 2024
    Inventors: Kyung ho KIM, Myung Il KANG, Sung Uk JANG, Kyung Hee CHO, Do Young CHOI
  • Patent number: 11932618
    Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: March 19, 2024
    Assignee: ILDONG PHARMACEUTICAL CO., LTD.
    Inventors: Hong Chul Yoon, Kyung Mi An, Myong Jae Lee, Jin Hee Lee, Jeong-geun Kim, A-rang Im, Woo Jin Jeon, Jin Ah Jeong, Jaeho Heo, Changhee Hong, Kyeojin Kim, Jung-Eun Park, Te-ik Sohn, Changmok Oh, Da Hae Hong, Sung Wook Kwon, Jung Ho Kim, Jae Eui Shin, Yeongran Yoo, Min Whan Chang, Eun Hye Jang, In-gyu Je, Ji Hye Choi, Gunhee Kim, Yearin Jun
  • Publication number: 20040163550
    Abstract: A cooking apparatus includes a heater mounting unit that mounts a heater on a reflecting plate in a simple manner and allows an internal construction of the cooking apparatus to be simple. The cooking apparatus also includes a cabinet, at least one heater mounted in the cabinet, a grill unit positioned on a top of the cabinet to allow food to be cooked while being laid thereon, at least one reflecting plate mounted behind the heater to reflect heat radiated toward a position behind the heater, and at least one elastic mounting unit to mount the heater on the reflecting plate through an elastic deformation thereof. Accordingly, an efficiency of production of the cooking apparatus may be improved, and the cooking apparatus may have a simple internal construction.
    Type: Application
    Filed: October 20, 2003
    Publication date: August 26, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Sung Han, Chul Kim, Yong-Woon Han, Seong-Deog Jang, Kyung-Hee Jang, Joo-Yeong Yeo, Han-Seong Kang
  • Patent number: 6259613
    Abstract: A power factor correction circuit is disclosed which is comprised of a boost converter that generates an output voltage to a secondary load according to operation of the switch. The circuit also includes a switching controller which multiplies together a secondary side error voltage of the boost converter and a voltage representative of the input current of the boost converter. The switching controller compares the multiplied voltage with a reverse sawtooth wave voltage, and controls the switch of the boost converter according to the comparison results.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: July 10, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woo Lee, Kyung-Hee Jang
  • Patent number: 6191565
    Abstract: A power factor compensation controller for use in a switching power supply having a switch, an inductor, and upper and lower reference signals that are proportional to an input voltage to the switching power supply includes a multiplier that multiplies an error signal and a signal representative of a current in the switch to produce a multiplier output signal. The power factor compensation controller further includes an adder that adds the multiplier output signal to the lower reference signal to produce an adder output signal and a comparator that compares the adder output signal to the upper reference signal to produce a comparator output signal.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: February 20, 2001
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Sang-Woo Lee, Kyung-Hee Jang
  • Patent number: 6175218
    Abstract: Disclosed is a Power Factor Correction (PFC) controller which comprises a boost converter, an error amplification unit, a calculator, and a switching driver. The error amplification unit reduces the error voltage of the output voltage of the boost converter to a specific reference voltage. The calculator receives first and second input voltages proportional to the input power of the converter and the output voltage of the error amplification unit, and outputs the voltage proportional to the first input voltage and the output voltage of the error amplification unit and inversely proportional to the second input voltage. The switching driver controls the switch to OFF when the voltage which detects the current flowing to switch of the boost converter becomes equal to the output voltage of the calculator, and controls the switch to ON when the zero current of the coil of the boost converter is detected.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: January 16, 2001
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Nak-Choon Choi, Kyung-Hee Jang, Maeng-Ho Seo
  • Patent number: 6084451
    Abstract: A pulse width modulation controller is shown which includes an error amplifier, a multiplying portion, an oscillator, a comparator, a flop-flop and a logic gate. The error amplifier receives an externally input feedback voltage and a first reference voltage in order to compare each voltage, and, in a current mode, the multiplying portion outputs a voltage which is proportional to the multiplication product of a voltage generated from a power switching unit and the difference between a second reference voltage and a voltage output from the error amplifier, and, in a voltage mode, outputs a voltage which is proportional to the multiplication product of a ground voltage and the difference between the second reference voltage and the voltage output from the error amplifier. The oscillator generates a clock signal and an inverse sawtooth signal. The comparator compares the inverse sawtooth signal with the output voltage of the multiplying portion.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: July 4, 2000
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Nak-choon Choi, Kyung-hee Jang, Sang-woo Lee