Patents by Inventor Kyung-Hwan Lee
Kyung-Hwan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11165018Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: GrantFiled: October 3, 2019Date of Patent: November 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Seok Han Park, Satoru Yamada, Jae Ho Hong
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Publication number: 20210335819Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.Type: ApplicationFiled: July 8, 2021Publication date: October 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji KANAMORI, Yong Seok KIM, Kyung Hwan LEE, Jun Hee LIM, Jee Hoon HAN
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Publication number: 20210335798Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.Type: ApplicationFiled: April 12, 2021Publication date: October 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Hwan LEE, Yong Seok KIM, Hyun Cheol KIM, Satoru YAMADA, Sung Won YOO, Jae Ho HONG
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Publication number: 20210319293Abstract: A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.Type: ApplicationFiled: April 7, 2021Publication date: October 14, 2021Inventors: Kyung Hwan LEE, Yong Seok KIM, Hyun Cheol KIM, Satoru YAMADA, Sung Won YOO, Jae Ho HONG
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Publication number: 20210249397Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.Type: ApplicationFiled: April 30, 2021Publication date: August 12, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji KANAMORI, Hyun Mog PARK, Yong Seok KIM, Kyung Hwan LEE, Jun Hee LIM, Jee Hoon HAN
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Patent number: 11088163Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.Type: GrantFiled: July 31, 2019Date of Patent: August 10, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
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Patent number: 11076309Abstract: A method for operating a terminal in a wireless communication system is provided. The method includes at least one of transmitting data to and receiving data from a primary cell using a first Radio Frequency (RF) path, and, when a secondary cell is deactivated, operating a second RF path to perform searching and measurement with respect to at least one target cell at a frequency different from a frequency of the primary cell.Type: GrantFiled: June 8, 2020Date of Patent: July 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Hee Lee, Byung-Wook Kim, Seong-Joon Kim, Jae-Ho Song, Myung-Hoon Yeon, Se-Jin Kim, Kyung-Hwan Lee
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Patent number: 11056645Abstract: A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.Type: GrantFiled: July 12, 2019Date of Patent: July 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Hwan Lee, Yong-Seok Kim, Jun-Hee Lim, Kohji Kanamori
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Patent number: 11024642Abstract: A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.Type: GrantFiled: July 11, 2019Date of Patent: June 1, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan Lee, Yong Seok Kim, Jun Hee Lim, Kohji Kanamori
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Patent number: 10998301Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.Type: GrantFiled: August 5, 2019Date of Patent: May 4, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Hyun Mog Park, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
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Publication number: 20210074914Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: ApplicationFiled: October 3, 2019Publication date: March 11, 2021Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
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Publication number: 20210047746Abstract: A home appliance includes a hairline. A manufacturing method for a home appliance including a hairline includes forming at least one plating layer on a base material; processing a transverse hairline on an upper surface of a plating layer by tilting a hairline processing wheel at a predetermined angle, and forming a coating layer on the hairline. A home appliance having corrosion resistance and anti-fingerprint properties is produced while generating a transverse hairline. In addition, it is possible not to perform a separate plating after hairline processing.Type: ApplicationFiled: November 9, 2018Publication date: February 18, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan LEE, Ji Young SONG, Kwang Joo KIM, In Hye HWANG, Jong Su OH
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Publication number: 20210036020Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
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Patent number: 10896728Abstract: In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.Type: GrantFiled: January 9, 2019Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Chang-Seok Kang, Yong-Seok Kim, Kyung-Hwan Lee
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Patent number: 10896711Abstract: A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.Type: GrantFiled: July 25, 2019Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan Lee, Seung Hyun Kim, Yong Seok Kim, Jun Hee Lim, Kohji Kanamori
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Patent number: 10888811Abstract: An air purifying unit in which leakage of air flowing between a filter and a blowing fan is significantly reduced, and an air cleaning/ventilation device including the same, are provided. In addition, there are an air cleaning/ventilation device detachably installed in a window, used as a ventilation device, and used as an indoor air cleaning device.Type: GrantFiled: January 4, 2017Date of Patent: January 12, 2021Assignee: COWAY CO., LTD.Inventors: Hyun-Jin Hong, Chan-Jung Park, Hyung-Tae Kim, Jong-Min Kim, Young-Kwang Choi, Kyung-Hwan Lee
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Patent number: 10861874Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.Type: GrantFiled: June 19, 2019Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Hwan Lee, Yong-Seok Kim, Jun-Hee Lim, Kohji Kanamori
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Publication number: 20200381619Abstract: A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.Type: ApplicationFiled: August 20, 2020Publication date: December 3, 2020Inventors: Kyung Hwan LEE, Chang Seok KANG, Yong Seok KIM, Kohji KANAMORI, Hui Jung KIM, Jun Hee LIM
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Patent number: 10852000Abstract: A household appliance including a control panel includes a body and a control panel provided on an outer side of the body, wherein the control panel includes a first panel formed by a process of extrusion of an aluminum (Al) material and provided with at least one surface thereof exposed to an outside thereof, and a second panel provided to be coupled to the first panel and made of the same material as the first panel.Type: GrantFiled: September 29, 2017Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo Hyoung Heo, Hyung-Jin Kim, Young Tae Kim, Kyung Hwan Lee, Yeong Hyeok Kim
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Publication number: 20200305012Abstract: A method for operating a terminal in a wireless communication system is provided. The method includes at least one of transmitting data to and receiving data from a primary cell using a first Radio Frequency (RF) path, and, when a secondary cell is deactivated, operating a second RF path to perform searching and measurement with respect to at least one target cell at a frequency different from a frequency of the primary cell.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Doo-Hee LEE, Byung-Wook KIM, Seong-Joon KIM, Jae-Ho SONG, Myung-Hoon YEON, Se-Jin KIM, Kyung-Hwan LEE