Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.

Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.

Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.

Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.

Abstract: An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.

Abstract: An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.

Abstract: An electronic component package includes a redistribution layer, an electronic component disposed on the redistribution layer, and an encapsulant encapsulating the electronic component. The electronic component has a trench formed in one side thereof.

Abstract: A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.

Abstract: A printed circuit board, a method of manufacturing a printed circuit board, and an electronic component module including a printed circuit board are provided. The printed circuit board includes a circuit board having a cavity, and a connection board including metal patterns, the connection board disposed in the cavity with the metal patterns disposed substantially vertically in the circuit board.

Abstract: An electronic component package and a method of manufacturing an electronic component package are provided. An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity, a redistribution layer disposed adjacent to the frame and electrically connected to the electronic component, and an encapsulation material encapsulating the electronic component and having an elastic modulus smaller than that of a material constituting the frame.

Abstract: A circuit board, and a package substrate and an electronic device that includes a circuit board are disclosed. The circuit board includes a core layer, a base pattern layer disposed on the core layer and a through-hole conductor that goes through the core layer, the base pattern layer including a circuit pattern that includes a conductive pad on the through-hole conductor, an insulator layer including at least one insulating layer stacked on the core layer and the base pattern layer, and a laminated pattern layer including a plurality of vias and a laminated circuit pattern, the plurality of vias penetrating the insulating layer, and the laminated circuit pattern being disposed on the insulating layer and including a plurality of via pads formed on the vias respectively.

Abstract: Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.

Abstract: Disclosed herein are a printed circuit board having a copper plated layer with an anchor shaped surface and roughness by forming the copper plated layer having an anisotropic crystalline orientation structure using a plating inhibitor at the time of forming the copper plated layer serving as a circuit wiring and using composite gas plasma and a dilute acid solution, and a method of manufacturing the same.

Abstract: Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.

Abstract: Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device.

Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board. According to a preferred embodiment of the present invention, there is provided a method for manufacturing a printed circuit board, including: preparing a base substrate; forming a carrier layer on the base substrate; forming a through via hole penetrating the carrier layer and the base substrate; forming a plating layer on the carrier layer and an inner wall of the through via hole; filling the through via hole with a conductive paste; removing a portion of the plating layer formed on the carrier layer; removing the carrier layer; and forming a circuit layer on the base substrate.

Abstract: A lighting apparatus using a light emitting diode (LED) package is disclosed. The lighting apparatus includes a lighting unit and a power unit. The lighting unit includes a plurality of light sources each including a light emitting diode (LED) package, and a lens element having a groove for receiving the LED package and a quadrangular plane for outputting light emitted from the LED package. The power unit is electrically connected with the lighting unit and supplies power for driving the lighting unit.

Abstract: A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board.