Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.

Abstract: An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor.

Abstract: The semiconductor device includes a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of CAM cells, a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nth word line, an n?1th word line and an n+1th word line to simultaneously program CAM cells electrically coupled to the n?1th word line, the nth word line and the n+1th word line, wherein the n?1th word line and an n+1th word line are adjacent to the nth word line and the selected CAM cells are electrically coupled to the nth word line.

Abstract: An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.

Abstract: The semiconductor memory device includes a memory cell array including a plurality of cell transistors, and a page buffer configured to perform an verification operation for verifying a program state of a selected cell transistor by sensing a voltage of a sense node connected to a selected bit line of the memory cell array through a bit line selection transistor, wherein a logic level corresponding to a voltage of the selected bit line is constantly maintained regardless of the program state of the selected cell transistor during the verification operation.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.

Abstract: The semiconductor device includes a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of CAM cells, a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nth word line, an n?1th word line and an n+1th word line to simultaneously program CAM cells electrically coupled to the n?1th word line, the nth word line and the n+1th word line, wherein the n?1th word line and an n+1th word line are adjacent to the nth word line and the selected CAM cells are electrically coupled to the nth word line.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.

Abstract: The semiconductor memory device includes a memory cell array including a plurality of cell transistors, and a page buffer configured to perform an verification operation for verifying a program state of a selected cell transistor by sensing a voltage of a sense node connected to a selected bit line of the memory cell array through a bit line selection transistor, wherein a logic level corresponding to a voltage of the selected bit line is constantly maintained regardless of the program state of the selected cell transistor during the verification operation.

Abstract: A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.