Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

Abstract: A semiconductor package includes a substrate, a die stack on the substrate, and connection terminals between the substrate and the die stack. The die stack includes a first die having a first active surface facing the substrate, the first die including first through electrodes vertically penetrating the first die, a second die on the first die and having a second active surface, the second die including second through electrodes vertically penetrating the second die, and a third die on the second die and having a third active surface facing the substrate. The second active surface of the second die is in direct contact with one of the first or third active surfaces.

Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.

Abstract: An image sensor including: a semiconductor substrate having a first region and a second region; an isolation region filling an isolation trench that partially penetrates the semiconductor substrate; a plurality of photoelectric conversion regions defined by the isolation region and forming a first hexagonal array on a plane that is parallel to a surface of the semiconductor substrate; and a plurality of microlenses respectively corresponding to the plurality of photoelectric conversion regions, and forming a second hexagonal array on the plane that is parallel to the surface of the semiconductor substrate.

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.