Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.

Abstract: Provided are a receiver and a transceiver for multi-level current-mode signaling, which together may reduce the number of bus lines and increase a data bandwidth. A transmitter transmits one reference current and a multi-level data current. On the basis of the reference current signal received from the transmitter, a receiver generates plural internal reference currents for determining the multi-level data current received from the transmitter, and converting the received multi-level data current into a data voltage having the desired level corresponding to the data that was transmitted.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) source driver for implementing a self burn-in test and a self burn-in test method are provided. The TFT-LCD source driver includes a self burn-in signal generator that generates a self burn-in signal and a burn-in load signal, a burn-in data generator that generates a burn-in data signal and a burn-in polarity control signal in response to the self burn-in signal and a clock signal. The TFT-LCD source driver also includes first and second switching units. The first switching unit transmits the burn-in load signal as an internal load signal, transmits the burn-in data signal as an internal digital data signal, and transmits the burn-in polarity control signal as an internal polarity control signal, in response to activation of the self burn-in signal. The second switching unit transmits outputs of output drivers to all channels of the TFT-LCD source driver in response to the internal load signal.

Abstract: Provided are a receiver and a transceiver for multi-level current-mode signaling, which together may reduce the number of bus lines and increase a data bandwidth. A transmitter transmits one reference current and a multi-level data current. On the basis of the reference current signal received from the transmitter, a receiver generates plural internal reference currents for determining the multi-level data current received from the transmitter, and converting the received multi-level data current into a data voltage having the desired level corresponding to the data that was transmitted.

Abstract: A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Abstract: A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.

Abstract: A level shifter changes an input signal whose level changes between a first voltage level and a ground voltage level into an output signal whose level changes between a second voltage level and the ground voltage level. The level shifter comprising a first input transistor and a second input transistor which receive the input signal and an inversion signal of the input signal, respectively; a first load transistor and a second load transistor, one side of each transistor being connected to the second voltage level; a first switch transistor connected between the first load transistor and the first input transistor, responding to the inversion signal; a second switch transistor connected between the second load transistor and the second input transistor, responding to the input signal; a first output unit for generating an output signal; and a second output unit that generates a complementary signal of the output signal.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) source driver for implementing a self burn-in test and a self burn-in test method are provided. The TFT-LCD source driver includes a self burn-in signal generator that generates a self burn-in signal and a burn-in load signal, a burn-in data generator that generates a burn-in data signal and a burn-in polarity control signal in response to the self burn-in signal and a clock signal. The TFT-LCD source driver also includes first and second switching units. The first switching unit transmits the burn-in load signal as an internal load signal, transmits the burn-in data signal as an internal digital data signal, and transmits the burn-in polarity control signal as an internal polarity control signal, in response to activation of the self burn-in signal. The second switching unit transmits outputs of output drivers to all channels of the TFT-LCD source driver in response to the internal load signal.

Abstract: A display device includes source drivers connected to a timing controller in a serial cascade. First through third buses are connected between the timing controller and a first source driver of source drivers. In a first period of time, a clock signal is transmitted via the first bus, a first operation control signal is transmitted via the second bus, a second operation control signal is transmitted via the third bus, and a polarity control signal is transmitted via the third bus. In a second period of time, the clock signal is transmitted via the first bus, the first operation control signal is transmitted via the second bus, and the second operation control signal is transmitted via the third bus. Source drivers generate a data initiation signal and a load signal using a combination of the logic levels of the operation control signals during each period.

Abstract: A level shifter changes an input signal whose level changes between a first voltage level and a ground voltage level into an output signal whose level changes between a second voltage level and the ground voltage level. The level shifter comprising a first input transistor and a second input transistor which receive the input signal and an inversion signal of the input signal, respectively; a first load transistor and a second load transistor, one side of each transistor being connected to the second voltage level; a first switch transistor connected between the first load transistor and the first input transistor, responding to the inversion signal; a second switch transistor connected between the second load transistor and the second input transistor, responding to the input signal; a first output unit for generating an output signal; and a second output unit that generates a complementary signal of the output signal.

Abstract: A level shifter circuit of the preferred embodiment can be used as a transfer gate driver of a memory circuit such as a DRAM. A pair of cross-coupled transistors receives a first potential. A plurality of transistors are coupled between the pair of cross-coupled transistors and a second potential. An output unit has a pull-down switch for providing an output signal of one of first, second and third potentials and are coupled to the pair of cross-coupled transistor and the plurality of transistors. The third potential has a potential between the first and second potentials.