Patents by Inventor Kyung Do Kim
Kyung Do Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240109839Abstract: The present invention relates to a novel compound exhibiting anti-inflammatory activity, and the compound of the present invention plays a key role in the generation of pro-inflammatory cytokines, thereby having excellent inhibitory activity against p38 MAPK, which is known to cause inflammatory diseases, and thus can be effectively used as an agent for treating inflammatory diseases.Type: ApplicationFiled: December 23, 2021Publication date: April 4, 2024Applicant: PRAZERTHERAPEUTICS INC.Inventors: Kyung-Soo INN, Nam-Jung KIM, Jong Kil LEE, Ga Yeong KIM, Kyeojin KIM, Donghwan KIM, Jimin DO, Chaewon SONG, Na-Rae LEE
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Publication number: 20230094071Abstract: An image sensing device includes a unit pixel configured to have a shape with first, second, third and fourth vertices where the second vertex and the third vertex are positioned in a diagonal direction of the unit pixel, a floating diffusion region disposed adjacent to the first vertex of the unit pixel, a transfer gate abutting on the floating diffusion region, a source region disposed adjacent to the second vertex of the unit pixel, a drain region disposed adjacent to the third vertex of the unit pixel, and a pixel transistor gate positioned between the source region and the drain region.Type: ApplicationFiled: July 21, 2022Publication date: March 30, 2023Inventors: Soon Yeol PARK, Hye Won MUN, Kyung Do KIM, Young Hwan PARK, Hyuk AN
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Patent number: 11168180Abstract: The present invention relates to a polyethylene glycol derivative and a preparation method thereof. A preparation process of a polyethylene glycol derivative, according to the present invention, may provide a novel polyethylene glycol derivative which can be utilized in various ways as a drug linker, and is appropriate and effective for mass production and is advantageous in reproducible mass production of high-quality products.Type: GrantFiled: November 6, 2018Date of Patent: November 9, 2021Inventors: Yong Gyu Jung, Bo Sung Kwon, Seung Hwan Kwak, Eun Rang Park, Kyung Do Kim, Hyun Sik Yun, Hyung Woo Lee, Young Bum Cho
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Publication number: 20200231749Abstract: The present invention relates to a polyethylene glycol derivative and a preparation method thereof. A preparation process of a polyethylene glycol derivative, according to the present invention, may provide a novel polyethylene glycol derivative which can be utilized in various ways as a drug linker, and is appropriate and effective for mass production and is advantageous in reproducible mass production of high-quality products.Type: ApplicationFiled: November 6, 2018Publication date: July 23, 2020Applicant: Hanmi Fine Chemical Co., Ltd.Inventors: Yong Gyu Jung, Bo Sung Kwon, Seung Hwan Kwak, Eun Rang Park, Kyung Do Kim, Hyun Sik Yun, Hyung Woo Lee, Young Bum Cho
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Patent number: 9355899Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.Type: GrantFiled: June 5, 2015Date of Patent: May 31, 2016Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong Ho Lee, Kyung Do Kim
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Publication number: 20150270167Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.Type: ApplicationFiled: June 5, 2015Publication date: September 24, 2015Inventors: Jong Ho LEE, Kyung Do KIM
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Patent number: 9076772Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.Type: GrantFiled: January 28, 2014Date of Patent: July 7, 2015Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong Ho Lee, Kyung Do Kim
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Publication number: 20150017773Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventor: Kyung Do KIM
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Patent number: 8928040Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).Type: GrantFiled: December 27, 2013Date of Patent: January 6, 2015Assignee: SK Hynix Inc.Inventor: Kyung Do Kim
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Patent number: 8878289Abstract: In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.Type: GrantFiled: December 7, 2012Date of Patent: November 4, 2014Assignee: SK hynix Inc.Inventor: Kyung Do Kim
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Publication number: 20140210058Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, SK hynix Inc.Inventors: Jong Ho LEE, Kyung Do KIM
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Patent number: 8728909Abstract: A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.Type: GrantFiled: August 16, 2011Date of Patent: May 20, 2014Assignee: Hynix Semiconductor Inc.Inventor: Kyung Do Kim
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Publication number: 20140110773Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).Type: ApplicationFiled: December 27, 2013Publication date: April 24, 2014Applicant: SK HYNIX INC.Inventor: Kyung Do KIM
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Patent number: 8642428Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).Type: GrantFiled: December 31, 2010Date of Patent: February 4, 2014Assignee: Hynix Semiconductor Inc.Inventor: Kyung Do Kim
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Patent number: 8610203Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.Type: GrantFiled: August 10, 2012Date of Patent: December 17, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kyung Do Kim
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Patent number: 8500225Abstract: The reinforcing component for a refrigerator, which is formed by mixing a base material as a synthetic resin material and a supplement component formed by arranging reinforcing fibers according to a pultrusion method, and combined with one or more portions of on one portion of an inner side of an outer case of the refrigerator to contact with foam, a corner of the bottom of the refrigerator or in a mechanic chamber of the refrigerator, an outer plate or an inner plate of a door of the refrigerator, and the interior of a side wall forming an inner space of the refrigerator can reduce the weight of the refrigerator while maintaining the strength.Type: GrantFiled: September 5, 2007Date of Patent: August 6, 2013Assignee: LG Electronics Inc.Inventors: Young-Bae Kim, Kyung-Do Kim, Hyung-Pyo Yoon
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Publication number: 20120306008Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Applicant: Hynix Semiconductor Inc.Inventor: Kyung Do KIM
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Publication number: 20120289024Abstract: A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.Type: ApplicationFiled: August 16, 2011Publication date: November 15, 2012Applicant: Hynix Semiconductor Inc.Inventor: Kyung Do KIM
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Patent number: 8263460Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operational gate and a dummy gate. A height of a gate electrode layer (conductive material) of the dummy gate is formed to be lower than that of a gate electrode layer of the operational gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the dummy gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.Type: GrantFiled: July 29, 2010Date of Patent: September 11, 2012Assignee: Hynix Semiconductor IncInventor: Kyung Do Kim
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Patent number: 8202781Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.Type: GrantFiled: July 7, 2011Date of Patent: June 19, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kyung Do Kim