Patents by Inventor Kyunghoon Min
Kyunghoon Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240068082Abstract: A deposition apparatus includes a mask, a mask frame, a stage disposed on a rear surface of the mask frame, and first to third external force applying parts disposed on the stage. Each of the first portion and the second portion includes a support and a driving part which moves the support. The first to third external force applying parts applies external force to the mask frame to control a shape of the mask frame.Type: ApplicationFiled: July 5, 2023Publication date: February 29, 2024Inventors: JUNHYEUK KO, MINGOO KANG, EUIGYU KIM, JONGBUM KIM, Sukha RYU, SANG MIN YI, KYUNGHOON CHUNG
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Publication number: 20240026040Abstract: A continuous polymerization reactor for super absorbent polymer is disclosed. The continuous polymerization reactor includes a cylindrical body; a discharge part with a diameter decreasing downward, positioned at a lower part of the body; an inlet positioned at an upper part of and connected to the body, into which a monomer composition is introduced; an outlet positioned at a lower part of the discharge part, from which hydrogel polymer is discharged; and a discharge valve opening or closing the outlet, wherein a ratio (H1/D1) of a sum (H1) of a height of the body and a height of the discharge part to a diameter (D1) of the body is 2 to 4. In addition, a continuous polymerization reaction system comprising the continuous polymerization reactor is also disclosed.Type: ApplicationFiled: June 20, 2022Publication date: January 25, 2024Applicant: LG CHEM, LTD.Inventors: Gyunhyeok AHN, Yoon Jae MIN, Seul Ah LEE, Gicheul KIM, Hee Kwan PARK, Kyunghoon MIN
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Publication number: 20220370959Abstract: Provided is a feed side spacer comprising a network structure, wherein the network structure includes a hexagonal eye, the hexagonal eye includes a pair of parallel portions parallel to a flow direction of a supply liquid, and an inclined portion disposed in a diagonal direction with respect to the flow direction of the supply liquid; the parallel portion has a length of 1 mm to 5 mm; the inclined portion has a length of 5.1 mm to 10 mm; and an angle formed by sides in contact with each other of the inclined portion is from 50° to 80°, and a separation membrane element comprising same.Type: ApplicationFiled: September 25, 2020Publication date: November 24, 2022Inventors: Taehyeong KIM, Dae Hun KIM, Taeyoung PARK, Phill LEE, Kyunghoon MIN
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Patent number: 11484841Abstract: Provided is a feed spacer having a three-layer structure, in which a set forming the feed spacer is formed in a three-layer structure, so that the set, which is in contact with a reverse osmosis membrane, convects raw water to a center of the structure of the feed spacer and a laminar flow velocity gradient is generated at the center to decrease a polarization phenomenon of a reverse osmosis filter module and minimize pressure loss, and a reverse osmosis membrane filter module including the feed spacer.Type: GrantFiled: October 17, 2018Date of Patent: November 1, 2022Assignee: LG CHEM, LTD.Inventors: Ayoung Lee, Dae Hun Kim, Bumjoo Kim, Chong Kyu Shin, Phill Lee, Kyunghoon Min
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Patent number: 11478750Abstract: Provided is a feed spacer, in which angles of strands are differently formed in one feed spacer according to a flow direction of raw water, so that a differential pressure decrease region and a recovery increase region are separated to perform multiple functions, and a reverse osmosis filter module including the feed spacer.Type: GrantFiled: November 13, 2018Date of Patent: October 25, 2022Assignee: LG CHEM, LTD.Inventors: Dae Hun Kim, Ayoung Lee, Kyunghoon Min, Bumjoo Kim, Ye Hoon Im
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Publication number: 20220193610Abstract: Provided is a feed spacer for reducing differential pressure of a reverse osmosis element, the feed spacer forming the reverse osmosis element, the feed spacer comprising a plurality of strands disposed in a mesh shape having predetermined intersection points, and wherein a vertical cross section of each of the strands has a rhombic shape such that a pressure loss of in the feed spacer is minimized by an effective flow of raw water at an interface of a reverse osmosis membrane, and a nozzle for forming the feed spacer.Type: ApplicationFiled: March 17, 2020Publication date: June 23, 2022Inventors: Taehyeong KIM, Taeyoung PARK, Phill LEE, Dae Hun KIM, Kyunghoon MIN
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Publication number: 20220111351Abstract: A method for preparing superabsorbent polymer is disclosed herein. In some embodiments, a method includes polymerizing a monomer composition to form a hydrogel polymer, wherein the monomer composition comprises a water soluble ethylenically unsaturated monomer and a polymerization initiator, drying and grinding the hydrogel polymer to prepare a base resin powder, surface cross-linking the base resin powder using a surface cross-linking agent to prepare surface cross-linked base resin powder, and hydrating the surface cross-linked base resin powder by pulse spraying water to prepare a superabsorbent polymer, wherein a scattering index of droplets generated during the pulse spraying is 5 to 10, and wherein the scattering index is calculated in accordance with the following Mathematical Formula 1.Type: ApplicationFiled: November 5, 2020Publication date: April 14, 2022Applicant: LG Chem, Ltd.Inventors: Kyu Pal Kim, Kyunghoon Min, Gicheul Kim, Yoon Jae Min, Ki Hyun Kim
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Publication number: 20210379104Abstract: Disclosed are a pharmaceutical composition containing isolated mitochondria as an effective component and uses of the composition. The pharmaceutical composition can restore the ATP synthesis capacity and antioxidant capacity of tenocytes damaged by inflammations to a normal tenocyte level. In addition, the pharmaceutical composition, when administered to damaged tenocytes, inhibits the expression of an apoptosis promoter, Bax, and increases the expression of an apoptosis inhibitor, Bcl-2. In addition, the pharmaceutical composition, when administered to damaged tenocytes, can restore the expression of MMP1 to a normal tenocyte level. Accordingly, uses of the pharmaceutical composition include prevention or treatment of tendinopathy in a subject.Type: ApplicationFiled: October 31, 2019Publication date: December 9, 2021Applicant: CHA UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Yong-Soo CHOI, Ji Min LEE, Mi Jin KIM, Kyunghoon MIN
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Patent number: 10967347Abstract: A chute type monomer dispenser is provided in the present disclosure. The chute type monomer dispenser includes a chute dispenser installed to be slanted in a direction of a polymerization apparatus, the chute dispenser is configured to inject a monomer to the polymerization apparatus through an injection pipe having an injection portion having an opening at an upper portion of the chute dispenser; and an injector configured to inject an initiator and a foaming agent to the injection portion.Type: GrantFiled: October 12, 2018Date of Patent: April 6, 2021Inventors: Sunyoung Kim, Young Cheol Jung, Ye Hoon Im, Youngsoo Song, Kyunghoon Min
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Publication number: 20210001295Abstract: A chute type monomer dispenser is provided in the present disclosure. The chute type monomer dispenser includes a chute dispenser installed to be slanted in a direction of a polymerization apparatus, the chute dispenser is configured to inject monomer to the polymerization apparatus through an injection pipe having an injection portion having an opening at an upper portion of the chute dispenser; and an injector configured to inject an initiator and a foaming agent to the injection portion.Type: ApplicationFiled: October 12, 2018Publication date: January 7, 2021Applicant: LG Chem, Ltd.Inventors: Sunyoung Kim, Young Cheol Jung, Ye Hoon Im, Youngsoo Song, Kyunghoon Min
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Publication number: 20200114313Abstract: Provided is a feed spacer, in which angles of strands are differently formed in one feed spacer according to a flow direction of raw water, so that a differential pressure decrease region and a recovery increase region are separated to perform multiple functions, and a reverse osmosis filter module including the feed spacer.Type: ApplicationFiled: November 13, 2018Publication date: April 16, 2020Inventors: Dae Hun KIM, Ayoung LEE, Kyunghoon MIN, Bumjoo KIM, Ye Hoon IM
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Publication number: 20200086276Abstract: Provided is a feed spacer having a three-layer structure, in which a set forming the feed spacer is formed in a three-layer structure, so that the set, which is in contact with a reverse osmosis membrane, convects raw water to a center of the structure of the feed spacer and a laminar flow velocity gradient is generated at the center to decrease a polarization phenomenon of a reverse osmosis filter module and minimize pressure loss, and a reverse osmosis membrane filter module including the feed spacer.Type: ApplicationFiled: October 17, 2018Publication date: March 19, 2020Inventors: Ayoung LEE, Dae Hun KIM, Bumjoo KIM, Chong Kyu SHIN, Phill LEE, Kyunghoon MIN
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Patent number: 8748972Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.Type: GrantFiled: June 18, 2013Date of Patent: June 10, 2014Assignee: Spansion LLCInventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
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Publication number: 20130277733Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.Type: ApplicationFiled: June 18, 2013Publication date: October 24, 2013Inventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
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Patent number: 8486782Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.Type: GrantFiled: December 22, 2006Date of Patent: July 16, 2013Assignee: Spansion LLCInventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
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Patent number: 8445372Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: GrantFiled: December 22, 2009Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
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Patent number: 8183623Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.Type: GrantFiled: March 29, 2011Date of Patent: May 22, 2012Assignee: Spansion LLCInventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Kyunghoon Min, Chi Chang
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Publication number: 20110175158Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Inventors: Chungho LEE, Hiroyuki KINOSHITA, Kuo-Tung CHANG, Amol JOSHI, Kyunghoon MIN, Chi CHANG
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Patent number: 7915123Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.Type: GrantFiled: April 20, 2006Date of Patent: March 29, 2011Assignee: Spansion LLCInventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Kyunghoon Min, Chi Chang
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Patent number: 7880221Abstract: A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.Type: GrantFiled: December 19, 2008Date of Patent: February 1, 2011Assignee: Spansion LLCInventors: Eunha Kim, Wen Yu, Minh-Van Ngo, Kyunghoon Min, Hiu-Yung Wong