Patents by Inventor L. Carl Christensen
L. Carl Christensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742946Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.Type: GrantFiled: February 18, 2022Date of Patent: August 29, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventor: L. Carl Christensen
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Publication number: 20230268993Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventor: L. Carl Christensen
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Patent number: 11736268Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.Type: GrantFiled: November 4, 2021Date of Patent: August 22, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: L. Carl Christensen, Reed P. Tidwell
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Patent number: 11722350Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.Type: GrantFiled: November 15, 2021Date of Patent: August 8, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: L. Carl Christensen, Ihab Francis
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Publication number: 20230155877Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.Type: ApplicationFiled: November 15, 2021Publication date: May 18, 2023Inventors: L. Carl Christensen, Ihab Francis
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Publication number: 20230134827Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Inventors: L. Carl Christensen, Reed P. Tidwell
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Patent number: 11626969Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.Type: GrantFiled: November 4, 2021Date of Patent: April 11, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: L. Carl Christensen, Reed P. Tidwell
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Patent number: 11621740Abstract: Systems and methods for operating a communication device. The methods comprise: receiving a carrier signal modulated with a modulation signal comprising a symbol conveyed in a symbol timing window; determining an energy value for each timeslot in the symbol timing window; combining the energy values to determine a combined energy value for each bit of the symbol in a manner in which the combined energy value is penalized if more than one timeslot of the symbol timing window comprises energy contained in the carrier signal; and generating a soft value for each bit of the sequence of bits by combining the combined energy value with a weight value, where the weight value is selected from a plurality of weight values based on a number of timeslots in the symbol timing window which comprises energy contained in the carrier signal.Type: GrantFiled: November 11, 2021Date of Patent: April 4, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: L. Carl Christensen, Ihab Francis
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Patent number: 9001925Abstract: A return-to-zero control signal for controlling a modulator can be generated from two separate streams. A first data stream can include a pulse for each logical one that appears in an input data stream, while a second data stream can include a pulse for each logical zero that appears in the input data stream. The first and second data streams can be combined in a manner that yields the return-to-zero control signal. The first and second data streams can be generated in digital circuitry, such as an FPGA, to minimize the analog path for generating the return-to-zero control signal.Type: GrantFiled: June 27, 2014Date of Patent: April 7, 2015Assignee: L-3 Communications Corp.Inventors: L. Carl Christensen, Bonnie A. Uresk, Justin D. Perry, Michael D. Rivers, John L. Metz, Larry H. Steinhorst