Patents by Inventor Lael H. Matthews
Lael H. Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126692Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock
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Patent number: 11868252Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.Type: GrantFiled: December 6, 2019Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock
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Patent number: 11670358Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.Type: GrantFiled: October 7, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson
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Patent number: 11393790Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.Type: GrantFiled: December 6, 2019Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Dale H. Hiscock, Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger
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Publication number: 20220028443Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson
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Patent number: 11145352Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.Type: GrantFiled: December 6, 2019Date of Patent: October 12, 2021Assignee: Micron Technology, Inc.Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson
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Publication number: 20210175208Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: Dale H. Hiscock, Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger
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Publication number: 20210173773Abstract: Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: Evan C. Pearson, John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock
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Publication number: 20210174859Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson