Patents by Inventor Lai Nguk Chin
Lai Nguk Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9679831Abstract: According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a frame tape.Type: GrantFiled: December 16, 2015Date of Patent: June 13, 2017Assignee: Cypress Semiconductor CorporationInventors: Lai Nguk Chin, Paphat Phaoharuhan, Sally Foong
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Publication number: 20170047272Abstract: According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a frame tape.Type: ApplicationFiled: December 16, 2015Publication date: February 16, 2017Applicant: Cypress Semiconductor CorporationInventors: Lai Nguk CHIN, Paphat PHAOHARUHAN, Sally FOONG
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Patent number: 9196608Abstract: Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.Type: GrantFiled: November 4, 2014Date of Patent: November 24, 2015Assignee: Cypress Semiconductor CorporationInventors: Sally Foong, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
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Publication number: 20150056726Abstract: Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.Type: ApplicationFiled: November 4, 2014Publication date: February 26, 2015Applicant: Spansion LLCInventors: Sally FOONG, Sheshasayee GADDAMRAJA, Teoh Lai BENG, Lai Nguk CHIN, Suthakavatin AUNGKUL
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Patent number: 8901756Abstract: Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.Type: GrantFiled: December 21, 2012Date of Patent: December 2, 2014Assignee: Spansion LLCInventors: Sally Foong, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
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Publication number: 20140175613Abstract: Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: Spansion LLCInventors: Sally FOONG, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul
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Patent number: 8680686Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.Type: GrantFiled: June 29, 2010Date of Patent: March 25, 2014Assignee: Spansion LLCInventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Thor Lee Lee, Sally Foong, Kevin Guan
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Patent number: 8357563Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.Type: GrantFiled: August 10, 2010Date of Patent: January 22, 2013Assignee: Spansion LLCInventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Koo Eng Luon, Sally Foong, Kevin Guan
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Publication number: 20120038059Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.Type: ApplicationFiled: August 10, 2010Publication date: February 16, 2012Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Koo Eng LUON, Sally FOONG, Kevin GUAN
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Publication number: 20110316158Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Thor Lee LEE, Sally FOONG, Kevin GUAN
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Patent number: 7932131Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.Type: GrantFiled: November 5, 2007Date of Patent: April 26, 2011Assignee: Spansion LLCInventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho
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Publication number: 20090115033Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.Type: ApplicationFiled: November 5, 2007Publication date: May 7, 2009Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho