Patents by Inventor Lakshmi Supriya

Lakshmi Supriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9604210
    Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarity, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, James C. Matayabas, Jr., Nirupama Chakrapani
  • Patent number: 9156973
    Abstract: A polymer article includes a meltprocessable blend of a melt-viscid fluoropolymer and a liquid crystalline polymer. Methods are presented for preparing a meltprocessable blend from a melt-viscid fluoropolymer and liquid crystalline polymer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 13, 2015
    Assignee: SAINT-GOBAIN PERFORMANCE PLASTICS CORPORATION
    Inventors: Lakshmi Supriya, Christopher M. Comeaux, Mathilde Leboeuf
  • Patent number: 9101931
    Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarly, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, James C. Matayabas, Jr., Nirupama Chakrapani
  • Publication number: 20150209780
    Abstract: A microelectronic package includes a die which may include MEMS and CMOS circuitry for analyzing a fluid. A defined path is provided for channeling fluid to the die. Rather than patterning depressions or physical channels in the package substrate, the defined paths comprise coatings that may channel the flow of liquids to the die for biological sensor type applications. The defined paths may comprise a wetting coating that has an affinity to fluids. Similarity, the defined paths may comprise a dewetting coating the tend to repel fluid surrounding the paths.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Applicant: Intel Corporation
    Inventors: Lakshmi Supriya, James C. Matayabas, JR., Nirupama Chakrapani
  • Patent number: 8592972
    Abstract: Methods are disclosed to process a thermal interface material to achieve easy pick and placement of the thermal interface material without lowering thermal performance of a completed semiconductor package. One method involves applying a non-adhesive layer on one or more surfaces of the thermal interface material, interfacing the thermal interface material with one or more components to interface the non-adhesive layer therebetween, and applying heat to alter the non-adhesive layer to increase thermal contact between the thermal interface material and the interfacing component(s).
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 26, 2013
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Jessica A Weninger, Leonel Arana, Lateef Mustapha
  • Publication number: 20130140014
    Abstract: Methods are disclosed to process a thermal interface material to achieve easy pick and placement of the thermal interface material without lowering thermal performance of a completed semiconductor package. One method involves applying a non-adhesive layer on one or more surfaces of the thermal interface material, interfacing the thermal interface material with one or more components to interface the non-adhesive layer therebetween, and applying heat to alter the non-adhesive layer to increase thermal contact between the thermal interface material and the interfacing component(s).
    Type: Application
    Filed: January 30, 2013
    Publication date: June 6, 2013
    Inventors: Lakshmi Supriya, Jessica A. Weninger, Leonel Arana, Lateef Mustapha
  • Publication number: 20130085220
    Abstract: A polymer article includes a meltproces sable blend of a melt-viscid fluoropolymer and a liquid crystalline polymer. Methods are presented for preparing a meltproces sable blend from a melt-viscid fluoropolymer and liquid crystalline polymer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Inventors: Lakshmi Supriya, Christopher M. Comeaux, Mathilde Leboeuf
  • Patent number: 8383459
    Abstract: Methods are disclosed to process a thermal interface material to achieve easy pick and placement of the thermal interface material without lowering thermal performance of a completed semiconductor package. One method involves applying a non-adhesive layer on one or more surfaces of the thermal interface material, interfacing the thermal interface material with one or more components to interface the non-adhesive layer therebetween, and applying heat to alter the non-adhesive layer to increase thermal contact between the thermal interface material and the interfacing component(s).
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Jessica Weninger, Leonel Arana, Lateef Mustapha
  • Patent number: 8183697
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy Ashton, II
  • Patent number: 8173259
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of functionalized nanaparticles on a substrate by immersing the substrate in at least one of a solvent and a polymer matrix, wherein at least one of the solvent and the polymer matrix comprises a plurality of functionalized nanoparticles; and forming a second layer of functionalized nanoparticles on the first layer of functionalized particles, wherein there is a gradient in a property between the first layer and the second layer.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Linda A. Shekhawat
  • Patent number: 8124517
    Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Daewoong Suh
  • Publication number: 20110240349
    Abstract: A multiple die structure includes a first die (110), a second die (120), a carbon nanotube (130) having a first end (131) in physical contact with the first die and having a second end (132) in physical contact with the second die, and an electrically conductive material (240) in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure (400, 500, 600, 900) in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.
    Type: Application
    Filed: June 17, 2011
    Publication date: October 6, 2011
    Inventors: Lakshmi Supriya, Gloria Alejandra Camacho-Bragado
  • Patent number: 8017498
    Abstract: A multiple die structure includes a first die (110), a second die (120), a carbon nanotube (130) having a first end (131) in physical contact with the first die and having a second end (132) in physical contact with the second die, and an electrically conductive material (240) in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure (400, 500, 600, 900) in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Gloria Alejandra Camacho-Bragado
  • Publication number: 20110074023
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 31, 2011
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy L. Ashton
  • Patent number: 7843075
    Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Anna M. Prakash, Tommy L. Ashton
  • Publication number: 20100276474
    Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Inventors: Lakshmi Supriya, Daewoong Suh
  • Patent number: 7727886
    Abstract: In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Omar J. Bchir
  • Publication number: 20100072617
    Abstract: A multiple die structure includes a first die (110), a second die (120), a carbon nanotube (130) having a first end (131) in physical contact with the first die and having a second end (132) in physical contact with the second die, and an electrically conductive material (240) in physical contact with the first end of the carbon nanotube and in physical contact with the first die. Forming a connection between the first die and the second die can include providing a connection structure (400, 500, 600, 900) in which the electrically conductive material is adjacent to the carbon nanotube, placing the connection structure adjacent to the first die and to the second die, and bonding the first die and the second die to the connection structure.
    Type: Application
    Filed: September 22, 2008
    Publication date: March 25, 2010
    Inventors: Lakshmi Supriya, Gloria Alejandra Camacho-Bragado
  • Patent number: 7651021
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmi Supriya, Ravi Nalla
  • Publication number: 20090317641
    Abstract: Methods are disclosed to process a thermal interface material to achieve easy pick and placement of the thermal interface material without lowering thermal performance of a completed semiconductor package. One method involves applying a non-adhesive layer on one or more surfaces of the thermal interface material, interfacing the thermal interface material with one or more components to interface the non-adhesive layer therebetween, and applying heat to alter the non-adhesive layer to increase thermal contact between the thermal interface material and the interfacing component(s).
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Lakshmi Supriya, Jessica Weninger, Leonel Arana, Lateef Mustapha