Abstract: A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor operation codes are partially decoded within an intermediate stage of an instruction pipe of the data processor to provide information on pending instructions. The information provided determines if a pending instruction will require either a full or a partial output line of information from the set associative cache. When the provided information from the instruction pipe indicates that an instruction will require a full output line of information to complete execution, the set associative cache provides the full output line of information. Otherwise, the set associative cache provides only a partial output line of information.

Abstract: In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i.e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.

Abstract: A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.

Abstract: An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.

Abstract: A memory is comprised of memory cells located at intersections of word lines and bit line pairs. The memory has a read mode in which data is read from a bit line pair selected by a column address. The data to be read is provided to bit line pairs by the memory cells which are coupled to a word line which has been selected to be enabled by a row address. In the write mode, data is written to a memory cell which is coupled to an enabled word line and which is coupled to a bit line pair into which data has been selected to be written. The pairs of bit lines are equalized in voltage in response to not only an address transition but also in response to a transition from the write mode to the read mode.

Abstract: A circuit for generating a pulse in response to an address transition using an input NOR gate to initiate the generation of the pulse. A delay circuit provides a delayed signal for actively terminating the pulse after a predetermined time period. An inhibit circuit is used to prevent the delayed signal from attempting to actively terminate the pulse when there has been another address transition, thereby saving power.

Abstract: An input buffer which can be used as a TTL to CMOS input buffer in a CMOS integrated circuit has a CMOS input inverter for receiving an external input signal. The typical threshold voltage of the P and N channel transistors is relatively low for high speed operation. At least one of the P and N channel transistors of the input inverter has the magnitude of its threshold voltage increased by applying appropriate back bias voltage in the well in which it resides.

Abstract: A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an externally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.

Abstract: A memory circuit, having an array with adjacent side-by-side portions, has half of the array precharged by precharging alternate portions. Pairs of adjacent portions have common sense amplifiers which receive signals from only the precharged portion of the pair of adjacent portions. The sense amplifiers are then arranged so that the conductor lines to the output pads are uninterrupted.

Abstract: An input buffer circuit for a memory uses two transistors interposed between a push-pull pair of transistors to control the enabling of the buffer in response to a chip write signal generated from a logical combination of chip select and write enable signals. A plurality of inverters which provide complementary signals to the push-pull transistors are disabled and prevented from using current by an interrupt transistor until the interrupt transistor receives the chip write signal.