Patents by Inventor Lalit Bharat

Lalit Bharat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure
    Patent number: 11256837
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sourav Kumar Sircar, Marc Heyberger, Manish Garg, Akash Khandelwal, Chunlong Pan, Ruchir Agarwal, Anurag Saran, Lalit Bharat, Namrata M Sadhankar, Manish Bhatia, Renuka Deshpande
  • Method and system for performing distributed timing signoff and optimization
    Patent number: 9633159
    Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vipul Parikh, Lalit Bharat, Shagufta Siddique, Prashant Sethia, Naresh Kumar