Patents by Inventor Lalla Fatima Drissi
Lalla Fatima Drissi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989443Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.Type: GrantFiled: May 12, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Chiara Cerafogli, Carla L. Christensen, Iolanda Del Villano, Lalla Fatima Drissi, Anna Scalesse, Maddalena Calzolari
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Patent number: 11922069Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.Type: GrantFiled: May 20, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete, Xiangang Luo, Xiaolai Zhu
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Patent number: 11922053Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.Type: GrantFiled: March 7, 2022Date of Patent: March 5, 2024Inventors: Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan, Giuseppe D'Eliseo
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Publication number: 20230376245Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete, Xiangang Luo, Xiaolai Zhu
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Publication number: 20230367504Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Chiara Cerafogli, Carla L. Christensen, Iolanda Del Villano, Lalla Fatima Drissi, Anna Scalesse, Maddalena Calzolari
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Publication number: 20230367495Abstract: Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Lalla Fatima Drissi, Anna Scalesse, Iolanda Del Villano, Maddalena Calzolari, Chiara Cerafogli, Carla L. Christensen
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Publication number: 20230367496Abstract: Methods, systems, and devices for block repurposing based on health metrics are described. The method may involve setting a storage state of a block of memory cells, the storage state corresponding to a storage density of the block of memory cells or an access mode of the block of memory cells. Further, the method may involve updating the storage state of the block of memory cells based on a health condition associated with the block of memory cells and accessing the block of memory cells based on the updated storage state of the block of memory cells.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Chiara Cerafogli, Carla L. Christensen, Iolanda Del Villano, Lalla Fatima Drissi, Anna Scalesse, Maddalena Calzolari
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Patent number: 11720489Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: September 2, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo Iaculo
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Patent number: 11675709Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: GrantFiled: October 5, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi
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Publication number: 20230068324Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Lalla Fatima Drissi, Doriana Tardio, Giuseppe D'Eliseo, Giuseppe Ferrari
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Publication number: 20220414003Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo Iaculo
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Patent number: 11455245Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 11, 2017Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo Iaculo
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Publication number: 20220188018Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Inventors: Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan, Giuseppe D'Eliseo
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Patent number: 11269545Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.Type: GrantFiled: December 21, 2017Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventors: Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan, Giuseppe D'Eliseo
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Publication number: 20220027284Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi
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Patent number: 11151052Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: GrantFiled: December 13, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Laculo, Lalla Fatima Drissi
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Publication number: 20210200672Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.Type: ApplicationFiled: December 29, 2020Publication date: July 1, 2021Inventors: Lalla Fatima Drissi, Giuseppe D'Eliseo, Paolo Papa, Massimo Iaculo, Carminantonio Manganelli
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Publication number: 20210182207Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Giuseppe D`Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Laculo, Lalla Fatima Drissi
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Publication number: 20210182189Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 11, 2017Publication date: June 17, 2021Inventors: Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo laculo
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Publication number: 20210141557Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.Type: ApplicationFiled: December 21, 2017Publication date: May 13, 2021Inventors: Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan, Giuseppe D'Eliseo