Abstract: A method and apparatus for incentivizing a user to update a device is provided herein. During operation, an update manager will determine a past history of performance problems specific to the device that needs updating. The device manager will also determine problems fixed with the update. A personalized message that mentions the past history of performance problems that are fixed with the update will be provided to the user along with a request to update the device.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Abstract: A method of forming a semiconductor package (50 and 52) includes providing a substrate (14) having a die pad and bond pads on a first surface (20) and conductive pads (66, 68 and 74) on a second surface (22). An integrated circuit (IC) die (38) is attached to the die pad and the first surface (20) of the substrate (14) is attached to a lead frame (26). The substrate (14) is electrically connected to the lead frame (26), and the IC die (38) is electrically connected to the substrate (14) and the lead frame (26). The IC die (14), the electrical connections (40, 42 and 44), a portion of the substrate (14) and a portion of the lead frame (26) are encapsulated with a mold compound (46), forming a stackable package (48). The conductive pads (66, 68 and 74) on the second surface (22) of the substrate (14) are not encapsulated by the mold compound (46).

Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.

Abstract: A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section of the mold chase (16) over a second end (18) of the tabs (10), such that the tabs (10) are anchored between the first and second sections (14, 16) of the mold chase, loading the first and second sections (14, 16) of the mold chase into a molding system (20) and performing a molding operation such that a plastic mold compound (22) is formed around the metal tabs (10) and an interconnect tablet (24) is formed. Then the first and second sections (14, 16) of the mold chase are removed from the molding system (20) and the interconnect tablet (24) is removed from the first and second sections (14, 16) of the mold chase.

Abstract: An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Abstract: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Abstract: A method and apparatus are disclosed herein for characterizing a network connection by receiving network connection parameters, receiving state variable information pertaining to the network connection according to the network connection parameters, sensing when the network connection is initiated according to the state variable information, and storing the state variable information.

Abstract: An improved method of bonding an insulated wire (14) that has one end connected to a first bond pad (16) to a second bond pad (18) includes moving a tip of a capillary (20) holding the bond wire (14) over the surface of the second bond pad (18) such that the bond wire (14) is rubbed between the capillary tip (20) and the second bond pad (18), which tears the bond wire insulation so that at least a portion of a metal core of the wire (14) contacts the second bond pad (18). The wire (14) is then bonded to the second pad (18) using thermocompression bonding. The tip of the capillary (20) is roughened to enhance the tearing of the bond wire insulation.

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.