Abstract: Systems, apparatuses, and methods related to isolating virtual machines in a memory device are described. A memory apparatus includes a memory device and a controller coupled to the memory device, wherein the controller is configured to provide a plurality of Peripheral Component Interconnect express (PCIe) functions of the memory device and isolate access to each of the plurality of PCIe functions via respective passwords and digital signatures created from host keys.

Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.

Abstract: Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory operably coupled to the controller, and security hardware operably coupled to the controller and to the main memory. The main memory can include a plurality of memory regions and at least one reserved memory region configured to store genuine backups of memory content stored in the plurality of memory regions. In operation, the security hardware is configured to measure memory content of the plurality of memory regions before startup, shutdown, and reset of the memory device; compare the measured value to an expected value; and direct the controller to replace the memory content with a genuine backup of the memory content stored in the at least one reserved memory region if the measured value and the expected value are not in accord.

Abstract: Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first range of physical memory addresses of a memory device, receiving a second address range for programming associated metadata to a second range of physical memory addresses of the memory device, determining whether the first address range is contiguous with the second address range, maintaining the second range of physical memory addresses for programming the metadata when it is determined that the second address range is contiguous with the first address range, and, when it is determined that the second address range is not contiguous with the first address range, remapping the second address range to a third range of physical memory addresses of the memory contiguous with the first range of physical memory addresses for programming the metadata.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory has a memory cache to store data corresponding to a received sector write operation, and a main memory comprising at least the designated memory block and a second memory block. A controller may reclaim at least one sector of the designated memory block and performing a write operation to write information from the memory cache in response to the received sector write operation to at least one sector of the second memory block.

Abstract: A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory blocks external to the array to store information in a single bit per cell mode, and a memory controller capable of allowing access to the array and the one or more flash memory blocks external to the array.

Abstract: A method and apparatus is described herein for compressing a binary image in memory and decompressing a portion memory in response to a request, without using a compression index table to find relocated compressed code. A binary image is traversed in windows. Each selected window is compressed to form compressed windows having a compressed portion and an available memory portion. Static data is backfilled in available memory portions to achieve efficient compression. Upon receiving a request to a specific physical address, the compressed portion of that physical location is decompressed and provided for execution without using a compression index table, as the compressed code portion was not relocated from its original physical location.

Abstract: An integrated microcontroller is embedded with non-volatile memory to enhance host processor execution by transferring the computational load of the filesystem from the host processor to the integrated microcontroller. The integrated microcontroller allows the physical nature of the non-volatile memory to be changed without changing the host software.

Abstract: A device and method for interfacing a processor to a non-volatile memory that may use a command based architecture to receive data from the processor and a long latency architecture that includes a microcode engine within the memory to control simple read, erase and program operations and further capable of controlling complex functions.

Abstract: Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset.

Abstract: Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory device includes a state machine capable of identifying the generic command, writing the specific flash memory commands to a buffer, and sequentially retrieving, interpreting and executing the buffered flash memory commands. The state machine can be configured as a microcontroller executing a state machine algorithm, and can be reprogrammed to correct design errors or to add new functionality to the flash memory device. The state machine algorithm can be stored in the flash memory device, and updated to interpret the same write cycle data in different ways. Accordingly, new functionality can be developed for the state machine long after its silicon has been designed and developed.

Abstract: System information prompting a reconfiguration of a target device that is part of the system is received, and in response to the information, the target device is reconfigured using configuration data for the target device that has been stored in non-volatile memory of a second self-configuring device that is part of the system.

Abstract: Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory device includes a state machine capable of identifying the generic command, writing the specific flash memory commands to a buffer, and sequentially retrieving, interpreting and executing the buffered flash memory commands. The state machine can be configured as a microcontroller executing a state machine algorithm, and can be reprogrammed to correct design errors or to add new functionality to the flash memory device. The state machine algorithm can be stored in the flash memory device, and updated to interpret the same write cycle data in different ways. Accordingly, new functionality can be developed for the state machine long after its silicon has been designed and developed.