Abstract: A system for coordinating error tracking, level setting and reporting among the various layers/components of a distributed storage system. Each component of the distributed system includes a trigger generation and response (TGR) utility, which generates an error tracking trigger (ETT), comprising: (1) an action that the initiator wants the stack's error tracking mechanisms to take; (2) a message that the initiator wants the stack to immediately post in its logs; and (3) a route/direction that the trigger is to be transmitted through the stack. The ETT is transmitted one layer at a time through the stack, and each intervening layer of the stack is equipped with a utility to examine the ETT and take the appropriate action(s), designated by the trigger. An error log is maintained by each layer of the stack and used to record information about the error and enable user determination of the source, timing and cause of errors.

Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.

Abstract: A method, apparatus, and computer instructions for controlling data flow. A control message is formed for the data flow in response to an event while the data flow is occurring. The control message includes a data type, an action, and a duration. The control message is sent to a receiver data processing system, wherein the receiver data processing system modifies the data flow to the data processing system using the control message.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: A method and structure for communicating in a communications network comprising at least one communication virtualizer; a plurality of network-attached store computers connected to the communication virtualizer, wherein the plurality of network-attached store computers are configured to appear as a single available network-attached store computer; and at least one client computer connected to the communication virtualizer.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: A method and system for handing-off TCP states in a communication network. Specifically, the present invention allows for handing-off TCP states between nodes in an associated network that is optimized for frequent handoff of TCP states. The handoff occurs between dynamically loadable modules that wrap around the TCP/IP stack located at a front-end server and a selected back-end server. A handoff protocol implemented by the loadable modules works within the kernel level of the existing TCP/IP code. As such, no changes to the existing TCP/IP code is necessary. The loadable modules at the front-end are able to select a back-end server depending on the content of the HTTP request, coordinate handing off TCP states, and forward packets to the back-end server. Loadable modules at the selected back-end modify response packets to reflect the proper TCP state of the front-end server.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.