Patents by Inventor Lance Williamson
Lance Williamson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11935574Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.Type: GrantFiled: October 7, 2021Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
-
Patent number: 11700729Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: GrantFiled: November 12, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Publication number: 20220077169Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Applicant: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Publication number: 20220028442Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: Micron Technology, Inc.Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
-
Patent number: 11205654Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: GrantFiled: August 25, 2019Date of Patent: December 21, 2021Assignee: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Patent number: 11189526Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: February 24, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
-
Patent number: 11170834Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.Type: GrantFiled: July 10, 2019Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
-
Publication number: 20210057428Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: ApplicationFiled: August 25, 2019Publication date: February 25, 2021Applicant: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
-
Publication number: 20210012824Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.Type: ApplicationFiled: July 10, 2019Publication date: January 14, 2021Applicant: Micron Technology, Inc.Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
-
Publication number: 20200194305Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
-
Patent number: 10600681Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: October 18, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
-
Publication number: 20190206726Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: October 18, 2018Publication date: July 4, 2019Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
-
Patent number: 10147638Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: December 29, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
-
Patent number: 6052264Abstract: A method and apparatus is disclosed for predicting capstan slipping in belt-driven tape cartridges. The method predicts the occurrence of capstan slip conditions between the belt capstan of a belt-driven tape cartridge and the rotating elastomeric drive roller of the tape drive. To predict capstan slip conditions, the method determines a critical velocity value corresponding to a critical slip condition based on a relationship between the drive force which rotates the cartridge belt capstan, and on the normal force of the drive roller against the cartridge belt capstan. A threshold velocity value corresponding to the drive and normal forces is selected at a point where the relationship between the drive and normal forces would not yet encounter the critical slip condition. The steady-state tape velocity is monitored during operation of the tape cartridge in the tape drive, and an imminent capstan slip indication is provided when the steady-state tape velocity reaches the threshold velocity value.Type: GrantFiled: December 18, 1997Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventor: Lance Williamson Curtis