Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.

Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.

Abstract: A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Abstract: A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.