Abstract: A circuit for implementing a full search block matching algorithm for coding video signals sequentially receives pixel values from a block of pixels in a current video frame and sequentially receives pixel values from a search area of a previous video frame. The circuit includes a plurality of processors for calculating in parallel a group of error functions corresponding to a group of positions of the block in the search area. The error functions are compared for determining the block position having the minimum error function.

Abstract: This processor is capable of real time processing of blocks of video pixel or other two-dimensional data to yield the two-dimensional Discrete Cosine Transform (DCT) thereof. The processor can be used as part of a video bandwidth or image compression system. The circuitry comprises a first one-dimensional DCT processor which simultaneously computes an entire row or column of vector inner products by using distributed arthmetic and using decimation-in-frequency to reduce the amount of memory capacity (ROM) required. Partial sums may also be used to further reduce ROM size. The one-dimensional transformed matrix from the first processor is stored in a transposition memory and the transpose of the stored matrix is applied to a second one-dimensional DCT processor of similar circuitry which computes the desired two-dimensional DCT of the input data matrix.