Patents by Inventor Lanzhong Wang

Lanzhong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050060314
    Abstract: One embodiment of the invention involves a data structure that is stored on a computer-readable medium comprising a sorted portion that contains a plurality of entries that are sorted into an order, an unsorted portion that contains a plurality of entries that have not been sorted, and a boundary that separates the sorted portion and the unsorted portion. The sorted portion of the data structure may be searched with O(logN) performance while an entry is added to the unsorted portion.
    Type: Application
    Filed: April 22, 2004
    Publication date: March 17, 2005
    Inventors: Lanzhong Wang, Richard Ferreri, John Applin
  • Patent number: 6823300
    Abstract: The inventive lightweight occurrence model uses a folded connectivity model which includes occurrence nodes. Each occurrence node includes occurrence specific data or a pointer to such data, a pointer to a parent occurrence node, and a pointer to a folded model describer. Thus, the information that would present in a full occurrence model can be included in the inventive lightweight occurrence model. The inventive model does not maintain duplicate information and requires less memory to store the inventive model. Since the inventive occurrence model is smaller than the full occurrence model, complex circuit designs, e.g. microprocessors, can be represented by the inventive lightweight occurrence model. Thus, low level characteristics of the design, e.g., timing delays, can be examined.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: November 23, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard Anthony Ferreri, Lanzhong Wang
  • Patent number: 6801884
    Abstract: The present invention allows traversal of net occurrences of a light weight occurrence model. In traversing down, a port iterator is preferably used, while in traversing up a port instance iterator is preferably used. The selected iterator is initialized with information about the current occurrence net from the inventive occurrence node that describes the occurrence net's owner and folded model describer. In traversing up, the iterator finds the next port that connects to the folded model net indicated by the describer used during initialization. Then, using information stored in the model, the iterator finds the occurrence net object that is one level higher in hierarchy than the original occurrence net object. In traversing down, the iterator finds the next port instance that connects to the folded model net indicated by the describer used during initialization.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: October 5, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard Anthony Ferreri, Lanzhong Wang
  • Patent number: 6625798
    Abstract: A methodology for translating multiple bit conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to realize a logic circuit design embodied by the non-Verilog HDL program. Conditional IF expressions occurring within the HDL program that are not recognized by Verilog HDL are processed so that they can be accordingly translated to Verilog HDL syntax. If the conditional IF expression is a multiple-bit expression, a binary operator statement having bit-wise binary operators, including two AND operators, one OR operator, and one NOT operator, that is equivalent to the conditional IF expression is created.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: September 23, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard A. Ferreri, Lanzhong Wang
  • Patent number: 6564354
    Abstract: A methodology for translating conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to prove out a logic circuit design. IF/CASE/COND (ICC) expressions occurring within the HDL program that are not recognized by Verilog HDL are categorized and accordingly translated to IF/CASE statements in Verilog HDL syntax. For ICC expressions that are part of a conditional or binary operator expression, a globally incremental variable that is representative of a corresponding variable of an ICC expression is created for each variable of the ICC expression. The ICC expression is then assigned to the globally incremental variable(s) which is placed in an always statement that is recognized by Verilog HDL. Synthesis can then be performed on the always statement by a processor to generate a logic circuit representative of the module of the non-Verilog HDL program.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: May 13, 2003
    Assignee: Hewlett Packard Development Company, L.P.
    Inventors: Lanzhong Wang, Paul Donald Hylander
  • Publication number: 20020112221
    Abstract: The present invention allows traversal of net occurrences of a light weight occurrence model. In traversing down, a port iterator is preferably used, while in traversing up a port instance iterator is preferably used. The selected iterator is initialized with information about the current occurrence net from the inventive occurrence node that describes the occurrence net's owner and folded model describer. In traversing up, the iterator finds the next port that connects to the folded model net indicated by the describer used during initialization. Then, using information stored in the model, the iterator finds the occurrence net object that is one level higher in hierarchy than the original occurrence net object. In traversing down, the iterator finds the next port instance that connects to the folded model net indicated by the describer used during initialization.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Inventors: Richard Anthony Ferreri, Lanzhong Wang
  • Patent number: 6119079
    Abstract: Methods and structure for storing log messages in a tokenized, international format and for presenting (viewing, printing, etc) the tokenized log message in a locally preferred native language. Log messages from a computing system or application are stored in an international tokenized format which remains constant regardless of the particular nation in which the system or application is operated. The tokenized format includes a message ID field which identifies a unique message and includes parameters values which are to replace variable portions, if any, of the identified message. A plurality of localized message catalog files are available to retrieve a localized native language string which corresponds to each tokenized message. The message ID field serves as an index to the localized catalog files. A viewer program then retrieves a localized text string message from a selected message catalog file replacing any variable portions identified therein with parameter values supplied in the tokenized message.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: September 12, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Lanzhong Wang, Charles W. Cairns, Jr.