Patents by Inventor Larisa Novakovsky
Larisa Novakovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900115Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: March 27, 2023Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Publication number: 20230401061Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: ApplicationFiled: March 27, 2023Publication date: December 14, 2023Inventors: Ashok RAJ, Andreas KLEEN, Gilbert NEIGER, Beeman STRONG, Jason BRANDT, Rupin VAKHARWALA, Jeff HUXEL, Larisa NOVAKOVSKY, Ido OUZIEL, Sarathy JAYAKUMAR
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Publication number: 20230325241Abstract: Embodiments for allocating shared resources are disclosed. In an embodiment, an apparatus includes a core and a hardware rate selector. The hardware rate selector is to, in response to a first indication that demand for memory bandwidth from the core has reached a threshold value, determine a delay value to be used to limit allocation of memory bandwidth to the core. The hardware rate selector includes a controller having a first counter to count a second indication of demand for memory bandwidth from the first core and a second counter to count expirations of time windows. The first indication is based on a difference between the first counter value and the second counter value.Type: ApplicationFiled: September 26, 2020Publication date: October 12, 2023Applicant: Intel CorporationInventors: Andrew J. HERDRICH, Yen-Cheng LIU, Venkateswara MADDURI, Krishnakumar K. GANAPATHY, Edwin VERPLANKE, Christopher GIANOS, Hanna ALAM, Joseph NUZMAN, Larisa NOVAKOVSKY
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Publication number: 20230315630Abstract: Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Hanna Alam, Yuval Bustan, Tomer Exterman, Dor Kahana, Larisa Novakovsky, Joseph Nuzman
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Patent number: 11614939Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: June 25, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Publication number: 20210357221Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: ApplicationFiled: June 25, 2021Publication date: November 18, 2021Inventors: Ashok RAJ, Andreas KLEEN, Gilbert NEIGER, Beeman STRONG, Jason BRANDT, Rupin VAKHARWALA, Jeff HUXEL, Larisa NOVAKOVSKY, Ido OUZIEL, Sarathy JAYAKUMAR
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Patent number: 11048512Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: March 28, 2020Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Patent number: 10990534Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.Type: GrantFiled: January 31, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Wei Chen, Eswaramoorthi Nallusamy, Larisa Novakovsky, Mark Schmisseur, Eric Rasmussen, Stephen Van Doren, Yen-Cheng Liu
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Publication number: 20200349312Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: ApplicationFiled: April 21, 2020Publication date: November 5, 2020Applicant: Intel CorporationInventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Patent number: 10775434Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.Type: GrantFiled: September 26, 2018Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Michael Mishaeli, Larisa Novakovsky, Edward Brazil, Alexander Gendler
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Patent number: 10725848Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.Type: GrantFiled: February 7, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
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Patent number: 10719326Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.Type: GrantFiled: February 1, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
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Patent number: 10628542Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: GrantFiled: July 1, 2017Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Publication number: 20200096569Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Michael Mishaeli, Larisa Novakovsky, Edward Brazil, Alexander Gendler
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Publication number: 20190243701Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
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Publication number: 20190171575Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.Type: ApplicationFiled: January 31, 2019Publication date: June 6, 2019Inventors: Wei CHEN, Eswaramoorthi NALLUSAMY, Larisa NOVAKOVSKY, Mark SCHMISSEUR, Eric RASMUSSEN, Stephen VAN DOREN, Yen-Cheng LIU
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Publication number: 20190102324Abstract: Cache behavior for secure memory repartitioning systems is described. Implementations may include a processing core and a memory controller coupled between the processor core and a memory device. The processor core is to receive a memory access request to a page in the memory device, the memory access request comprising a first guarded attribute (GA) indicator indicating whether the page is a secure page belonging to an enclave, determine whether the first GA indicator matches a second GA indicator in a cache line entry corresponding to the page, the cache line entry comprised in a cache, and responsive to a determination that the first GA indicator does not match the second GA indicator, apply an eviction policy to the cache line entry based on whether the cache line is indicated as a dirty cache line and accessing second data in the memory device for the page.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Meltem Ozsoy, Krystof C. Zmudzinski, Larisa Novakovsky, Julius Mandelblat, Francis X. McKeen, Carlos V. Rozas, Ittai Anati, Ilya Alexandrovich
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Patent number: 10175992Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.Type: GrantFiled: October 1, 2016Date of Patent: January 8, 2019Assignee: Intel CorporationInventors: Leon Polishuk, Pavel Konev, Larisa Novakovsky, Julius Mandelblat
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Publication number: 20190005160Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Inventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Patent number: 10157136Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.Type: GrantFiled: March 31, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Leeor Peled, Joseph Nuzman, Larisa Novakovsky