Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.

Abstract: A process is provided for planarization of an insulation layer, e.g., of silicon dioxide, on a semiconductor wafer, e.g., of silicon, and having a surface with a downwardly stepped chemically mechanically polished arrangement of metal lines in the insulation layer between intervening insulation portions. A first pattern portion of metal lines is separated by intervening insulation portions and defines a first pattern factor having a first value, and an adjacent second pattern portion of metal lines is separated by intervening insulation portions and defines a second pattern factor having a second value different from the first value. The second pattern portion is at a step depth relative to the insulation layer surface different from that of the first pattern portion relative to such layer surface.

Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the steps of providing a semiconductor wafer including a dielectric layer formed on the wafer, the dielectric layer having vias formed therein and placing the wafer in a deposition chamber. The method further includes depositing a metal on the wafer to fill the vias wherein the metal depositing is initiated when the wafer is at a first temperature and the depositing is continued while heating the wafer to a target temperature which is greater than the first temperature.

Abstract: Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.