Abstract: A 3-dimensional (3D) video rendering device may convert a first left view video of a decompressed 3D video having a first frame rate to generate a second left view video having a second frame rate, and convert a first right view video having the first frame rate to generate a second right view video having the second frame rate. The second left view video having a particular pixel resolution may be converted by the 3D video rendering device to generate a third left view video having full pixel resolution of the decompressed 3D video. The second right view video having the particular pixel resolution may be converted to generate a third right view video having the full pixel resolution. The 3D video rendering device may generate a sequence of video frames for 3D video display based on the third left view video and the third right view video.

Abstract: An audio processing device may estimate noise effects at a particular location based on noise measurement data corresponding to one or more noise sources. The audio processing device may modify one or more output audio content transmitted by the audio processing device to that particular location such that the modification may cancel the estimated noise effects at the particular location, at time when the output audio streams are received at that location. The noise effects estimation may also be based on audio reception measurement data at the particular location. The noise measurement data and/or the audio reception measurement data may be generated by audio capturing devices placed at or near noise sources, and/or at or near the particular location, respectively. The noise measurement data and/or the audio reception measurement data may be communicated to the audio processing device using wired and/or wireless connections.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

Abstract: A video processing system may receive a current raw video frame and may estimate motion between the current frame and a previous frame to determine motion vectors (mv). Based on the same mvs, motion compensated (MC) noise reduction may be performed and MC frame rate conversion (FRC) may generate a new frame. The previous frame may be noise reduced and/or a raw video frame. A MC frame may be generated based on the previous video frame and the mvs. Noise reduction may comprise blending the current raw frame with the MC frame. A blending factor may be determined based on similarity between pixels of the current video frame and MC pixels of the previous frame. The mvs may be scaled for FRC. Noise reduction may be performed in parallel and/or prior to the FRC depending on whether raw or noise reduced frames are utilized.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: Methods and apparatus for encoding image data to facilitate subsequent insertion of local image data. Also methods and apparatus for inserting image data, e.g., at local broadcast stations, without having to fully decode a received encoded bitstream. The encoding methods involve treating images to be encoded as a plurality of distinct, non-overlapping image regions or segments for encoding purposes. Image segments which are designated for use for local data insertion are not used as reference data for motion compensated prediction purposes when generating motion vectors to represent image areas, e.g., the area representing the main picture, which are outside the local data insertion segments. Because image segments which may be replaced are not used as reference data for image segments which will not be replaced, unintentional prediction errors which might otherwise result from replacing one or more image segments as part of a local data insertion operation are avoided.

Abstract: In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

Abstract: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.

Abstract: An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived.

Abstract: A method and apparatus of frame rate conversion where descriptive information relating to an input video signal is transmitted to the frame rate converter along with the input signal. The descriptive information is used to interpolate frames, allowing the interpolator to make pixel analysis using the descriptive information relating to the original signal. The descriptive information is derived by a compositor/scaler and is transmitted to the frame rate converter with the composited/scaled signal. There may be multiple input signals that are composited to make a final composited video output such as a picture-in-picture display. The information may be transmitted in-band with the video signal received by the frame rate converter. Alternatively, the descriptive information may be transmitted in a separate stream in a side-band manner. In another embodiment, the descriptive information may be transmitted to the frame rate converter separate from the video input source as commands or packets.

Abstract: A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.

Abstract: A method and apparatus for reduced complexity video and image processing with special chroma handling are disclosed. Frame-type decisions are made on a video stream made up of a sequence of frames. A first subset of the frames are selected to be monochrome and generated without chroma data. A second subset of the frames are selected to be in color and generated with chroma components. In one embodiment, the first subset of frames includes odd frames and the second subset of frames includes even frames in the video stream. Under higher video frame rates, the lack of color in every other frame is not visible to the end viewer. Accordingly, subsequent processing of the output video stream permits luma-only processing of many frames in the video stream, extensively reducing the amount of computation.

Abstract: An image processing method for frame rate conversion, comprising: receiving a stream of input pictures at an input frame rate, at least some of the input pictures being new pictures, the new pictures appearing within the stream of input pictures at an underlying new picture rate; generating interpolated pictures from certain ones of the input pictures; outputting a stream of output pictures at an output frame rate, the stream of output pictures including a blend of the new pictures and the interpolated pictures, the interpolated pictures appearing in the stream of output pictures at an average interpolated picture rate; and causing a variation in the average interpolated picture rate in response to detection of a variation in the underlying new picture rate.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A method for reducing memory bandwidth in a video decoder begins by performing a data reduction operation on a decoded first coded image to produce a second set of image data. The second set of image data stored and is selectively used for subsequent image decoding, thereby reducing the memory bandwidth. The data reduction operation can include image downsampling, wherein the pixel density is reduced by a factor of two in each of the vertical and horizontal directions.

Abstract: A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

Abstract: A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.