Abstract: A system and method for controlling a power amplifier using a programmable ramp circuit involves receiving an input bias current at a programmable ramp circuit, generating an output bias current based on the input bias current using the programmable ramp circuit, and transmitting the output bias current from the programmable ramp circuit to a power amplifier for amplifying a radio frequency signal.

Abstract: A system and method for controlling a power amplifier using a programmable ramp circuit involves receiving an input bias current at a programmable ramp circuit, generating an output bias current based on the input bias current using the programmable ramp circuit, and transmitting the output bias current from the programmable ramp circuit to a power amplifier for amplifying a radio frequency signal.

Abstract: A BFSK demodulator comprises a three-channel frequency-to-voltage converter, an information signal inputting the first-channel frequency-to-voltage converter, a converted information signal inputting the second-channel frequency-to-voltage converter, wherein outputs of first and second channel frequency-to-voltage converter are connected with a capacitor, a output voltage signal produced by the first and second frequency-to-voltage converters and the capacitor, inputting into a positive terminal of the comparator after high frequency noise filtering through a first low-pass filter, a carrier signal inputs into the third-channel frequency-to-voltage converter; and an output from the third-channel frequency-to-voltage converter connected to a capacitor; and a reference voltage signal is produced after high frequency noise filtering through a second low-pass filter, producing a demodulated signal after comparing the information voltage signal with the reference voltage.

Abstract: The present invention is directed to a circuit that may be used to protect other circuits from Electrostatic Discharge (“ESD”). A circuit of the present invention comprises a transmission line that couples a source with a circuit that is being protected. A transistor, with an emitter, a collector, and a base, is coupled in reverse mode between an electrical ground and the circuit being protected. This circuit may be used in applications using high frequencies, such as 1 GHz or higher.

Abstract: The present invention is directed to a circuit that may be used to protect other circuits from Electrostatic Discharge (“ESD”). A circuit of the present invention comprises a transmission line that couples a source with a circuit that is being protected. A transistor, with an emitter, a collector, and a base, is coupled in reverse mode between an electrical ground and the circuit being protected. This circuit may be used in applications using high frequencies, such as 1 GHz or higher.

Abstract: A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Abstract: A system for controlling slew rate in a motor control circuit for a motor comprises a high side switching device coupled to a coil of the motor, the high side switching device operable to control a voltage excitation signal applied at the coil. The system also comprises a high side slew rate control circuit operable to control a slew rate of the voltage excitation signal. The high side slew rate control circuit includes: an amplifier having an output coupled to an input of the high side switching device, a current sink coupling a first input of the amplifier to ground, a capacitor further coupling the first input of the amplifier to ground, and a feedback path from an output of the high side switching device to a second input of the amplifier.

Abstract: A clamping circuit (100) is provided for controlling an external switch, using a control signal, in response to monitoring a voltage at a first node. When the voltage at the first node exceeds a certain voltage, the clamping circuit (100) closes the external switch to complete a current path to reduce the voltage at the first node. The clamping circuit (100) includes a voltage divider circuit, a first device, a second device, a current mirror circuit, and a switch. The voltage divider circuit, which may be implemented using a resistor (30) and a resistor (32), is coupled between the first node and a fourth node and generates a divider voltage at a third node that is proportional to the voltage at the first node. The first device and the second device may be implemented using a first bipolar junction transistor (38) and a second bipolar junction transistor (40), respectively.

Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: A circuit to control a motor having phase inputs. A respective control signal for each phase input of the motor is generated such that each phase input is cyclically driven and undriven. Additionally, changes at each phase input relative to a reference potential are measured, and changes at each phase input during time intervals in which noise is expected are ignored: timing information based on the measured changes at the phase inputs is generated, and timing information to carry out the step of generating a respective control signal is used.

Abstract: A motor drive control circuit for operation in both linear and PWM modes includes a switchably connected compensation network. The compensation network has a capacitor that provides control loop compensation. To avoid transient effects during the settling time upon transitions from one mode to the other, the switch connecting the compensation network in the circuit is closed only during linear operation and not during PWM mode operation. When the switch is open, the capacitor holds a previously attained potential that is reapplied to the circuit when the switch is again closed.

Abstract: A motor drive control circuit for operation in the PWM mode includes a feedack circuit from a resistor for sensing motor coil current modified to switchably connect the resistor to the drive input in accordance with operation of a sample-hold switch. The sample-hold switch is controlled to sample a signal proportional to motor coil current only at the middle of the coil current rise during each PWM ON time, thus providing a reliable indication of average coil current. A signal storage capacitor connected in the feedback circuit receives the sampled signal and retains it for use in feedback control throughout PWM operation until the next sample.

Abstract: A stator coil driver circuit for a brushless DC motor, with an improved current mirror, is disclosed. The improved current mirror has a first transistor which conducts current and a second transistor configured to mirror the current of the first transistor. Additionally, the improved mirror circuit includes a unity gain amplifier connected in between the gates of the first and second transistor. The effect of the unity gain transistor is to provide for a faster turn-off of the second transistor and reduce oscillation of the circuit.