Patents by Inventor Larry Bert Brenner

Larry Bert Brenner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8996834
    Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Michael Edward Lyons, Bruce G. Mealey, James Bernard Moody
  • Patent number: 7992150
    Abstract: A computer implemented method, a data processing system, and computer usable program code for improving thread posting efficiency in a multiprocessor data processing system are provided. Aspects of the present invention first receive a set of threads from an application. The aspects of the present invention then group the set of threads with a plurality of processors based on a last execution of the set of threads on the plurality of processors to form a plurality of groups. The threads in each group in the plurality of groups are all last executed on a same processor. The aspects of the present invention then wake up the threads in the plurality of groups in any order.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 7676809
    Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Basu Vaidyanathan, Larry Bert Brenner
  • Patent number: 7653909
    Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: January 26, 2010
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 7555636
    Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: June 30, 2009
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Publication number: 20080294864
    Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Inventors: Larry Bert Brenner, Michael Edward Lyons, Bruce G. Mealey, James Bernard Moody
  • Patent number: 7448036
    Abstract: A system and method for thread scheduling with a weak preemption policy is provided. The scheduler receives requests from newly ready work. The scheduler adds a “preempt value” to the current work's priority so that it is somewhat increased for preemption purposes. The preempt value can be adjusted in order to make it more, or less, difficult for newly ready work to preempt the current work. A “less strict” preemption policy allows current work to complete rather than interrupting the current work and resume it at a later time, thus saving system overhead. Newly ready work that is queued with a better priority than the current work is queued in a favorable position to be executed after the current work is completed but before other work that has been queued with the same priority of the current work.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Mysore Sathyanarayana Srinivas, James W. Van Fleet
  • Publication number: 20080271029
    Abstract: Thread scheduling with a weak preemption policy is provided. The scheduler receives requests from newly ready work. The scheduler adds a “preempt value” to the current work's priority so that it is somewhat increased for preemption purposes. The preempt value can be adjusted in order to make it more, or less, difficult for newly ready work to preempt the current work. A “less strict” preemption policy allows current work to complete rather than interrupting the current work and resume it at a later time, thus saving system overhead. Newly ready work that is queued with a better priority than the current work is queued in a favorable position to be executed after the current work is completed but before other work that has been queued with the same priority of the current work.
    Type: Application
    Filed: July 7, 2008
    Publication date: October 30, 2008
    Applicant: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Mysore Sathyanarayana Srinivas, James W. Van Fleet
  • Patent number: 7437541
    Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: October 14, 2008
    Assignee: International Business Machiens Corporation
    Inventor: Larry Bert Brenner
  • Publication number: 20080235686
    Abstract: A computer implemented method, a data processing system, and computer usable program code for improving thread posting efficiency in a multiprocessor data processing system are provided. Aspects of the present invention first receive a set of threads from an application. The aspects of the present invention then group the set of threads with a plurality of processors based on a last execution of the set of threads on the plurality of processors to form a plurality of groups. The threads in each group in the plurality of groups are all last executed on a same processor. The aspects of the present invention then wake up the threads in the plurality of groups in any order.
    Type: Application
    Filed: May 29, 2008
    Publication date: September 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Larry Bert Brenner
  • Publication number: 20080133846
    Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.
    Type: Application
    Filed: January 22, 2008
    Publication date: June 5, 2008
    Inventor: Larry Bert Brenner
  • Patent number: 7370331
    Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 7308690
    Abstract: A system and method is provided for using a kernel exit routine, performed when a parent process exits, to efficiently remove zombie child processes. The kernel exit routine also re-parents active child processes to a standard system process, such as the init process. When the kernel exit routine re-parents the active child process to the init process, the child process is flagged indicating that the child's original parent process has already exited. A kernel routine, such as the swapper process, periodically cleans up flagged processes that have exited. In this manner, although active child processes are still re-parented to init, the init process is no longer burdened with the task of waiting on such processes when they exit.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Luke M. Browning
  • Patent number: 7228243
    Abstract: An application implementing a high resolution monotonic system clock is provided. A kernel increments a value called a generation number. The generation number is used to determine what state the high and low resolution time values are in. The kernel next stores a low resolution time value. Then, if a time adjustment is occurring, the kernel updates the high resolution time value by updating the origin date. The kernel then increments the generation number a second time. The providing application receives a request for time from another application. The providing application determines a first value for the generation number and compares a low resolution time value and high resolution time value and determines the maximum value of the two. The providing application then gets a second value for the generation number and compares the second value of the generation number to the first value of the generation number.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 7191098
    Abstract: Method and system for detecting and reporting an excessive period of interrupt disablement in operating system programming in a data processing system. A method for detecting and reporting an excessive period of disablement in operating system programming in a data processing system includes determining, at a plurality of scheduled times, if an operating system task is running disabled for interrupts, and reporting an excessive disablement if the operating system task runs disabled for interrupts for a predefined number of consecutive scheduled times.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 7080379
    Abstract: A method, system and apparatus for integrating a system task scheduler with a workload manager are provided. The scheduler is used to assign default priorities to threads and to place the threads into run queues and the workload manager is used to implement policies set by a system administrator. One of the policies may be to have different classes of threads get different percentages of a system's CPU time. This policy can be reliably achieved if threads from a plurality of classes are spread as uniformly as possible among the run queues. To do so, the threads are organized in classes. Each class is associated with a priority as per a use-policy. This priority is used to modify the scheduling priority assigned to each thread in the class as well as to determine in which band or range of priority the threads fall. Then periodically, it is determined whether the number of threads in a band in a run queue exceeds the number of threads in the band in another run queue by more than a pre-determined number.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Dean Joseph Burdick
  • Patent number: 7065766
    Abstract: Apparatus and methods for load balancing fixed priority threads in a multiprocessor system are provided. The apparatus and methods of the present invention identify unbound fixed priority threads at the top of local run queues. A best fixed priority thread is then identified and its priority checked against the priorities of threads executing on processors of the node. A set of executing threads that may be displaced by the best fixed priority thread is identified. The lowest priority executing thread from the set is then identified and the best fixed priority thread is moved to displace this lowest priority executing thread.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 20, 2006
    Assignee: International Business Machines Corporation
    Inventor: Larry Bert Brenner
  • Patent number: 6993767
    Abstract: An apparatus and methods for periodic load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Luke Matthew Browning
  • Patent number: 6986140
    Abstract: An apparatus and methods for periodic load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Luke Matthew Browning
  • Patent number: 6981260
    Abstract: Apparatus and methods are provided for selecting a thread to dispatch in a multiple processor system having a global run queue associated with each multiple processor node and having a local run queue associated with each processor. If the global run queue and the local run queue associated with the processor performing the dispatch are both not empty, then the highest priority queue is selected for dispatch, as determined by examining the queues without obtaining a lock. If one of the two queues is empty and the other queue is not empty, then the non-empty queue is selected for dispatch. If the global queue is selected for dispatch but a lock on the global queue cannot be obtained immediately, then the local queue is selected for dispatch. If both queues are empty, then an idle load balancing operation is performed. Local run queues for other processors at the same node are examining without obtaining a lock.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Luke Mathew Browning