Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.

Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.

Abstract: An application implementing a high resolution monotonic system clock is provided. A kernel increments a value called a generation number. The generation number is used to determine what state the high and low resolution time values are in. The kernel next stores a low resolution time value. Then, if a time adjustment is occurring, the kernel updates the high resolution time value by updating the origin date. The kernel then increments the generation number a second time. The providing application receives a request for time from another application. The providing application determines a first value for the generation number and compares a low resolution time value and high resolution time value and determines the maximum value of the two. The providing application then gets a second value for the generation number and compares the second value of the generation number to the first value of the generation number.

Abstract: Method and system for detecting and reporting an excessive period of interrupt disablement in operating system programming in a data processing system. A method for detecting and reporting an excessive period of disablement in operating system programming in a data processing system includes determining, at a plurality of scheduled times, if an operating system task is running disabled for interrupts, and reporting an excessive disablement if the operating system task runs disabled for interrupts for a predefined number of consecutive scheduled times.

Abstract: A computer implemented method, a data processing system, and computer usable program code for improving thread posting efficiency in a multiprocessor data processing system are provided. Aspects of the present invention first receive a set of threads from an application. The aspects of the present invention then group the set of threads with a plurality of processors based on a last execution of the set of threads on the plurality of processors to form a plurality of groups. The threads in each group in the plurality of groups are all last executed on a same processor. The aspects of the present invention then wake up the threads in the plurality of groups in any order.

Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: A method and system in a multiprocessor data processing system (MDPS) that enable efficient load balancing between a first processor with idle processor cycles in a first MCM (multi-chip module) and a second busy processor in a second MCM, without significant degradation to the thread's execution efficiency when allocated to the idle processor cycles. A load balancing algorithm is provided that supports both stealing and borrowing of threads across MCMs. An idle processor is allowed to “borrow” a thread from a busy processor in another memory domain (i.e., across MCMs). The thread is borrowed for a single dispatch cycle at a time. When the dispatch cycle is completed, the thread is released back to its parent processor. No change in the memory allocation of the borrowed thread occurs during the dispatch cycle.

Abstract: A system, apparatus and method of reducing cache thrashing in a multi-processor with a shared cache executing a disruptive process (i.e., a thread that has a poor cache affinity or a large cache footprint) are provided. When a thread is dispatched for execution, a table is consulted to determine whether the dispatched thread is a disruptive thread. If so, a system idle process is dispatched to the processor sharing a cache with the processor executing the disruptive thread. Since the system idle process may not use data intensively, cache thrashing may be avoided.

Abstract: A system, apparatus and method of reducing adverse performance impact due to migration of processes from one processor to another in a multi-processor system are provided. When a process is executing, the number of cycles it takes to fetch each instruction (CPI) of the process is stored. After execution of the process, an average CPI is computed and stored in a storage device that is associated with the process. When a run queue of the multi-processor system is empty, a process may be chosen from the run queue that has the most processes awaiting execution to migrate to the empty run queue. The chosen process is the process that has the highest average number of CPIs.

Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.

Abstract: A method, computer program product, and a data processing system for queuing threads among a plurality of processors in a multiple processor system having a plurality of multi-processor modules is provided. A first thread to be processed is received and is identified as part of an existing process. A search for an idle processor is performed. The search is restricted to processors of a first multi-processor module associated with the existing process.

Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.

Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.

Abstract: A method for assembling swap blocks of virtual pages for transfer between a backing store and physical memory in a data processing system. The method includes segregating all virtual pages resident in physical memory between an active list and an inactive list. Virtual pages are then assigned to the inactive list by groups where each page in a group belongs to a single owning task or object. From a group, virtual pages are assigned to a swap block based upon correlation of most recent use. The swap block may then be paged out in a single operation to a backing store. A list of the group members is kept to permit page in to physical memory upon reference to a member of the swap block.