Abstract: The invention features a method of screening for an agent that inhibits intracellular phosphodiesterase 10A activity, comprising administering an agent to striatal medium spiny neurons and submaximally activating adenylate cyclase, administering an agent to striatal medium spiny neurons and submaximally activating guanylate cyclase, measuring cAMP generation and cGMP generation in the cells, and calculating the cAMP EC200 and the cGMP EC200, wherein the agent is identified as a PDE10A inhibitor if the ratio of cAMP EC200/cGMP EC200 is comparable to the ratio produced by administration of papaverine under the same assay conditions. Also featured are rat PDE10A polynucleotide and polypeptide sequences.

Abstract: Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are "Owned" and "Unowned." The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Abstract: Memory controller logic for concurrently obtaining memory access locality information by cycle type for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. The monitoring logic further includes a programmable cycle control register and comparison logic to condition the page access counters for specific memory cycle types, such as coherency cycles, reads, writes, copyback cache cycles, etc.

Abstract: A method implemented in hardware to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought.

Abstract: A method, implemented in hardware, to successively obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within a specified address range within system memory. Whenever the processing node generates a transaction requiring access to a memory address within the specified address range, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. The specified address range is defined by an address value contained within a range counter.

Abstract: A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

Abstract: An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories.

Abstract: A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time.

Abstract: An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories.

Abstract: This invention relates to modified Yarrowia lipolytica LEU2 gene promoters; modified Y. lipolytica LEU2 genes comprising such modified Y. lipolytica LEU2 gene promoters; and vectors comprising such modified Y. lipolytica LEU2 genes. This invention also relates to vectors comprising a Y. lipolytica DNA sequence LEU2 genes. This invention also relates to vectors comprising a Y. lipolytica DNA sequence sufficient for integrative transformation of Y. lipolytica; vectors which comprise a nucleotide sequence coding for a polypeptide and a promoter functional in Y. lipolytica operably linked thereto; E. coli transformants which comprise vectors according to this invention; Y. lipolytica transormants which comprise an expression vector according to this invention; methods of producing Y. lipolytica transformants comprising multiple integrated expression vectors; strains of Y. lipolytica useful in the preparation of such transformants; methods of producing polypeptides with certain of the Y.

Abstract: Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals.

Abstract: System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough.

Abstract: Nonvolatile memory is provided on each module of a computer system including one or more modules with each module including a plurality of components including JTAG technology. A test bus operable in accordance with the 1149.1 standard is included in the computer system and is arranged to access the nonvolatile memory. Boundary scan information for the components on a module and also additional information, preferably fully describing all JTAG related characteristics and operations, is stored in the nonvolatile memory. A JTAG bus system is then able to access the module memory and obtain all information required to fully implement JTAG operations for the module.

Abstract: A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.