Abstract: A method and apparatus for decoding of frequency inversion based scramblers is disclosed. A quadrature amplitude modulation detector determines the frequency of the tone used for inverting the scrambled signal by determining which of a plurality of quadrature detector pairs, each using a different conversion frequency, has the greatest magnitude difference between the quadraturely related signals. The frequency of the quadrature pair with the greatest difference is the frequency of the inverting tone during the inverting period of time. This frequency information is used to generate a reinversion tone to unscramble the scrambled signal.

Abstract: A cryptographic apparatus for encrypting and decrypting digital words includes a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus. The storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm. A mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.

Abstract: A method and means for maintaining continuous bit synchronization of data transmitted from a remote unit through a base unit to a landline unit is disclosed. An input data stream at a first bit rate, such as digitized or encrypted speech, is interleaved with a plurality of signalling words, and transmitted over an RF channel at a second bit rate. The base site recovers the clock of the received data, strips off the signalling word, modifies the bit rate of the received data, and adjusts the recovered clock rate to provide an output data stream which is in bit synchronization with the input data stream and within a predetermined modem specification. The encrypted data is then sent over landlines to a decryption unit which requires bit synchronization.

Abstract: A full duplex speakerphone employing adaptive filters and having application in radiotelephone systems is disclosed. To cancel acoustic feedback echo of the receive signal, a representation of the receive signal is subtracted from the transmit signal generated by the speakerphone microphone. The adaptive filter receive signal representation coefficents are modified when the receive signal is detected. Likewise, to cancel electronic echo of the transmit signal, a representation of the transmit signal is subtracted from the receive signal. The adaptive filter transmit signal representation coefficients are modified when the transmit signal is detected.

Abstract: An improved radiotelephone includes a unique microprocessor and peripheral devices for controlling the operation of portable or mobile radio transceivers in a cellular-type radiotelephone system. The microprocessor is coupled by a data interface unit and synchronization unit to the radio transceiver for transmitting and receiving Manchester-coded supervisory signalling having a 10 KHz bit rate. The microprocessor is also coupled by a unique self-clocking serial data bus and unique interface adapters to the radio transceiver for controlling the operating frequency, audio signals and transmitted RF signal thereof, to a keyboard for sampling the keys thereof, an off-hook switch and display for displaying telephone numbers, and to serial number and telephone number memories for accessing the stored serial and telephone numbers assigned to the radiotelephone.

Abstract: A unique method and apparatus for efficiently assigning duplex radio channels and scanning duplex radio channels assigned to mobile and portable radiotelephones in a cellular communications system is described. Each cell includes a base station radio having a signalling channel and a plurality of voice channels, and a base site controller adapted to utilize the methods embodying the present invention for controlling communications paths to mobile and portable radiotelephones. The base station radios include a signalling transceiver operable on the signalling channel, a plurality of voice transceivers each operable on a voice channel, and a scanning receiver for sampling the signal strength of active radiotelephones. Transmitters of signalling transceivers and voice transceivers are combined and coupled to an omnidirectional antenna; and the receivers of the signalling transceiver, voice transceivers and scanning receiver are couplable to one or more of six sector antennas.

Abstract: A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus. Data signals are routed between the various blocks of the microprocessor by selectively interconnecting the three buses in response to control signals provided by ALU and control programmable logic arrays (PLA). The ALU and control PLA's decode program instructions loaded in instruction register (IR) to provide the appropriate control signals for executing each instruction.

Abstract: A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal.

Abstract: A unique interface adapter is described which includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from a data signal transmitted on two forward data signals. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether an output register or a data direction register is to be loaded in response to the read/write signal with the data portion of the data signal. The binary states of the data direction register determine which ones of the interface signals are to be output signals, and enable corresponding output register signals to be applied to the interface signals by way of transmission gates.