Patents by Inventor Larry Christopher Wall

Larry Christopher Wall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PACKAGED TRANSISTOR WITH CHANNELED DIE ATTACH MATERIALS AND PROCESS OF IMPLEMENTING THE SAME
    Publication number: 20240079320
    Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Mitch FLOWERS, Erwin COHEN, Alexander KOMPOSCH, Larry Christopher WALL
  • Packaged transistor having die attach materials with channels and process of implementing the same
    Patent number: 11830810
    Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 28, 2023
    Assignee: WOLFSPEED, INC.
    Inventors: Mitch Flowers, Erwin Cohen, Alexander Komposch, Larry Christopher Wall
  • Packaged Transistor with Channeled Die Attach Materials and Process of Implementing the Same
    Publication number: 20210351121
    Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 11, 2021
    Inventors: Mitch Flowers, Erwin Cohen, Alexander Komposch, Larry Christopher Wall
  • Integrated circuit self-monitored burn-in
    Patent number: 8405412
    Abstract: An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: March 26, 2013
    Assignee: LSI Corporation
    Inventors: Ross A. Kohler, Richard J. McPartland, Larry Christopher Wall, Wayne E. Werner
  • Integrated Circuit Self-Monitored Burn-In
    Publication number: 20100271064
    Abstract: An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 28, 2010
    Inventors: Ross A. Kohler, Richard J. McPartland, Larry Christopher Wall, Wayne E. Werner
  • Enhanced boundary-scan method and apparatus providing tester channel reduction
    Publication number: 20040199838
    Abstract: An integrated circuit or other electronic circuitry is tested by arranging device pins into multiple-pin groups, and permitting the device pins of the group to share a single tester channel of a piece of test equipment. More particularly, a group comprising a plurality of device pins of the electronic circuitry is designated, and assigned to one of a plurality of tester channels in the test equipment. A test may then be performed on the electronic circuitry, via the assigned tester channel, utilizing at least a subset of the device pins in the designated multiple-pin group. Advantageously, the invention allows high pin count integrated circuits to be tested using inexpensive test equipment platforms.
    Type: Application
    Filed: March 19, 2003
    Publication date: October 7, 2004
    Inventors: Paul William Rutkowski, Larry Christopher Wall