Abstract: An apparatus and method for preventing haze growth on a surface of a substrate are disclosed. The apparatus includes a container operable to store a substrate and a gas source coupled to the container. The gas source is operable to dispense a gas into the container in order to prevent a haze from growing on a surface of the substrate.

Abstract: A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.

Abstract: A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A method for forming an interconnect structure on a semiconductor wafer (114) begins by placing the wafer (114) in a process chamber (100). The process chamber (100) contains a titanium (Ti) target (102) having a thin titanium nitride (TiN) layer (104) formed thereon. An argon-based plasma (106) is used to sputter the layer (104) off of the target (102) and onto a top surface of the water (114) to form an Argon Uniquely Sputtered Titanium Nitride (AUSTiN) layer (116) which has a nitrogen concentration gradient therethrough. After forming the layer (116), an argon-nitrogen plasma (107) is initiated to reform the titanium nitride (TiN) layer (104) on the target and complete the interconnect structure by forming a top stoichiometric or near stoichiometric titanium nitride layer (118) over the layer (116).

Abstract: In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.

Abstract: A via 42 is formed in an ILD layer 40 of a semiconductor device 30, using an etch chemistry which is highly selective to an underlying transition metal oxy-nitride film 38. In one form, film 38 is a TiO.sub.x N.sub.y film which is graded in nitrogen and oxygen concentration, being nitrogen rich at the bottom and oxygen reach at the top of the film. One method for forming TiO.sub.x N.sub.y is to sputter deposit a titantium layer 34 onto the semiconductor device using a titanium target 52. Using the same target, a TiN layer 36 is deposited by flowing nitrogen into the deposition chamber. Consequently, a TiN layer 58 is deposited onto target 52. The TiN layer 58 is then sputtered off the target onto the semiconductor device until eventually pure titanium is again being sputtered onto the device. The resulting deposited film has a grade titanium concentration, which is then oxidized to form the graded TiO.sub.x N.sub.y film.

Abstract: An ion source of the side extraction type which includes auxiliary electrodes surrounding the cathode at the ends of the anode, and insulators surrounding the auxiliary electrodes and electrically isolating them from the anode. The auxiliary electrodes essentially define the ends of the discharge chamber, leaving the anode confined to the cylindrical surface surrounding the filament. Each insulator is made up of an inner insulator and an outer insulator with an annular space defined between them. The inner and outer insulators are each in the form of a cylinder with a radially extending flange formed at one end, and interfit with the anode and with each other such that cylindrical spaces are defined between the outer flange portion and the anode and between the inner and outer flange portions. These and other features contribute to improve the electrical isolation between the auxiliary electrode and the anode, prolong source life, and improve beam purity.