Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: A socket-less test board and a clamp for clamping an integrated circuit to the socket-less test board is disclosed. The test board includes a recess region for receiving an integrated circuit to be tested. The clamp includes a base structure with a recess region to accommodate the integrated circuit and a heat sink that is positioned in contact with the package of the integrated circuit. Mounting and fastening elements mount and fasten the clamp to the test board, holding the integrated circuit in place during electrical testing.

Abstract: A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

Abstract: A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters enter a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

Abstract: A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a reference unit coupled to provide a reference temperature to the control logic unit and a reference sensor coupled to provide a signal having a reference frequency to the control logic unit. The reference unit and the reference sensor are located near each other. The control logic unit is configured to correlate the reference frequency received from the reference sensor with the reference temperature received from the reference unit. The control logic unit is further configured to determine the temperature of each of the remote temperature sensors based on this correlation, and also configured to determine the maximum temperature of all of the temperature sensors.

Abstract: An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.

Abstract: An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: An improved response reordering technique for use in a southbridge device or I/O hub or similar devices are provided. Non-posted read requests are received from at least one requestor, and upstream commands are transmitted based on the non-posted read requests. Each of the upstream commands is uniquely identified by a command tag. When response data is received in reply to previously transmitted commands, responses are transmitted to the at least one requestor based on the response data. Transmitting the responses comprises reordering the received response data by accessing a buffer of the southbridge device. The buffer stores the received response data and has a plurality of buffer elements that are each uniquely assigned to one of the command tags.

Abstract: A watercraft lift having hydraulic cylinders secured to lift towers and pivot axles located above the water surface to raise and lower a cradle that is secured to a surrounding support framework with lift frames that radiate from the framework and cradle corners. Length adjustable legs depend from the framework to appropriately elevate and position the cradle and framework relative to the surface level of the waterway. Brace arms extend from the lift towers to the forward ends of the support framework. The cylinders rotate between a parallel condition to the top of the cradle, when fully elevated, and an inclined condition, when the cradle is fully lowered. The cylinders remain at all times substantially above the water.

Abstract: A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

Abstract: A multi-processor computer system includes at least a first and second processor coupled to a host bus. The first processor accesses a first set of registers using a first plurality of addresses over the host bus. A second processor accesses a second set of registers using the first plurality of addresses over the host bus. A first integrated circuit forms a bridge between the host bus and an input/output bus. The first integrated circuit receives access requests for the first and second sets of registers from the first and second processors, respectively. A second integrated circuit, coupled to the input/output bus, includes a first and a second local interrupt controller, the first and second sets of registers being part of the first and second local interrupt controllers.

Abstract: A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.

Abstract: Asynchronous and isochronous data is transferred over a bus connecting a first device and a second device. Data is selectably transferred over the bus in either asynchronous priority mode or isochronous priority mode. Asynchronous priority mode gives priority to transfer of the asynchronous data and isochronous priority mode gives priority to transfer of the isochronous data. In addition, data transferred over the bus is selectably transferred in either whole-bus mode: in which the entire data bus transfers data in one direction or in or half-bus mode in which portions of the data bus may transfer data in different directions.

Abstract: A computer system includes a first processor integrated circuit. A first bridge integrated circuit is coupled to the processor via a host bus. The computer system includes an interconnection bus that couples the first bridge circuit to a second bridge circuit. The interconnection bus provides a first transfer mode for asynchronous data and a second transfer mode for isochronous data. The interconnection bus provides for a maximum latency and a guaranteed throughput for asynchronous and isochronous data.

Abstract: A USB host controller provides transaction type status signals indicating USB activity type. The status signals include a bulk status bit signal indicative of bulk activity on a USB, a control status bit signal indicative of control activity on the USB, an isochronous status bit signal indicative of isochronous activity on the USB and an interrupt status bit signal indicative of an acknowledged interrupt on the USB. In addition a programmable mask register is provided for masking any or all of the status bits. The status bits may be combined and provided as a single signal indicative of USB activity.

Abstract: A wavetable audio synthesis system includes a simplified burst data transmission interface and a modified wavetable data structure in a system memory to transfer wavetable data from the system memory to a wavetable audio synthesis device with reduced hardware complexity. The system memory is configured to store voice data in patches including a plurality of voice data samples beginning at an initial address and extending through a plurality of ramp voice data samples to a starting loop address. The voice data in the patches then includes a plurality of looping voice data samples from the starting loop address to an ending loop address. The voice data patches are extended by repeating the voice data samples beginning with the sample at the starting loop address and extending toward the samples at the ending loop address. The number of repeated samples extend for a number of samples equal to the size of a burst transfer.

Abstract: Power consumption is conserved in a computer system by, instead of forcing a processor to change from the stop clock state to a fully operational state, allowing the processor to transition from the stop clock state to the stop grant state. The stop grant state allows snoops so that the processor handles subsequent bus cycles and snoops that take place during the bus cycles. Following the snoops, the processor transitions back from the stop grant state to the stop clock state. In one embodiment, an automatic control circuit is connected to a processor in a computer system. When the processor is in the stop clock state, the automatic control circuit responds to a bus request, not by transitioning to the fully operational state, but instead by transitioning from the stop clock state to the snoopable stop grant state in which the processor clock is operating.

Abstract: Asynchronous and isochronous data is transferred over a bus connecting a first device and a second device. Data is selectably transferred over the bus in either asynchronous priority mode or isochronous priority mode. Asynchronous priority mode gives priority to transfer of the asynchronous data and isochronous priority mode gives priority to transfer of the isochronous data. In addition, data transferred over the bus is selectably transferred in either whole-bus mode in which the entire data bus transfers data in one direction or in or half-bus mode in which portions of the data bus may transfer data in different directions.

Abstract: A wavetable cache for an audio synthesizer which synthesizes music signals from voice data in a pooled memory uses a vertical architecture cache to communicate data from the memory to an audio signal processor. The vertical architecture cache includes a substantially limited number of queues, corresponding to only a fraction of the voices stored in the main memory and processed in the audio signal processor. A plurality of samples are transferred in a batch mode from the memory via a system bus to a queue. The samples are subsequently processed and accumulated for the entire plurality of samples by the audio signal processor. The limited number of queues are shared among the different voices in a round-robin fashion.