Patents by Inventor Larry J. Koudele
Larry J. Koudele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111445Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Patent number: 11940892Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device; aggregating temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature; responsive to beginning to program a block residing on the memory device, associating the block with the block family; and in response to the aggregate temperature being greater than or equal to a specified threshold temperature value: performing a soft closure of the block family; initializing an extension timer; continuing to program data to the block; and performing a hard closure of the block family in response to one of the extension timer reaching an extension time value or the block family satisfying a hard closure criteria.Type: GrantFiled: July 19, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Steven S. Williams
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Patent number: 11941277Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.Type: GrantFiled: March 6, 2023Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Shane Nowell, Michael Sheperek, Larry J. Koudele, Vamsi Pavan Rayaprolu
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Patent number: 11934666Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure.Type: GrantFiled: May 27, 2022Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventors: Larry J. Koudele, Bruce A. Liikanen
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Patent number: 11923021Abstract: A memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. A temperature level associated with the memory unit is determined. Based on the time after program and the temperature level, a set of read offset values to apply in executing the read operation is determined. The read operation is executed using the set of read offset values.Type: GrantFiled: January 5, 2023Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Larry J. Koudele
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Patent number: 11915776Abstract: A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.Type: GrantFiled: September 12, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Mustafa N Kaynak, Larry J Koudele
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Patent number: 11908536Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device then adjusts a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before the second programming pass of the programming operation is performed on the memory cell.Type: GrantFiled: November 7, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
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Publication number: 20240045605Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. In some embodiments, the processing device accesses a matrix of threshold voltage offset bins, where a first dimension of the matrix is temperature and a second dimension of the matrix is a temporal voltage shift (TVS) amount. The processing device measures a temperature value based on a reference temperature value for a block family. The processing device measures a TVS value of a voltage level within one or more memory cell of the block family. The processing device retrieves, from the matrix, a threshold voltage offset bin based on the reference temperature value and the TVS value and reads data from any page of the block family via application of a threshold voltage offset, specified by the threshold voltage offset bin, to a base read level voltage.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz
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Patent number: 11886726Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.Type: GrantFiled: December 6, 2021Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Patent number: 11853556Abstract: A system including a memory device and a processing device, the processing device to identify a first temperature level of a first set of memory blocks associated with the memory device, and a second temperature level of a second set of memory blocks associated with the memory device, and determine that a condition is satisfied based on a comparison of the first temperature level, the second temperature level, and an adjustable threshold level. In response to the condition being satisfied, the processing device is to combine the first set of memory blocks and the second set of memory blocks to generate a combined set of memory blocks.Type: GrantFiled: June 6, 2022Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Steven Michael Kientz, Larry J. Koudele, Shane Nowell, Michael Sheperek, Bruce A. Liikanen
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Patent number: 11842061Abstract: A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including initializing a block family associated with the memory device and measuring an opening temperature of the memory device at initialization of the block family. Responsive to programming a page residing on the memory device, the operations further include associating the page with the block family. The operations further include determining a temperature metric value by integrating, over time, an absolute temperature difference between the opening temperature and an immediate temperature of the memory device. The operations further include closing the block family in response to the temperature metric value being greater than or equal to a specified threshold temperature value.Type: GrantFiled: August 19, 2020Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz
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Patent number: 11837291Abstract: One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.Type: GrantFiled: January 31, 2022Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Michael Sheperek, Larry J. Koudele, Shane Nowell
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Patent number: 11817152Abstract: A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.Type: GrantFiled: August 22, 2022Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
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Patent number: 11789640Abstract: A data structure that identifies a characteristic of a region that is located between programming distributions of the memory device and that corresponds to read level thresholds at the region is determined. An estimator type is selected from a plurality of estimator types corresponding with the data structure. A read level threshold of the read level thresholds is estimated using the selected estimator type. A read operation is performed at the memory device using the read level threshold estimated using the selected estimator type.Type: GrantFiled: May 10, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
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Patent number: 11755478Abstract: A set of two or more block families associated with a bin boundary of a first voltage bin is identified. A determination of at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families based on values of a data state metric for each of the plurality of block families. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.Type: GrantFiled: February 8, 2022Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Mustafa N. Kaynak, Shane Nowell
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Patent number: 11742027Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.Type: GrantFiled: May 27, 2022Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
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Patent number: 11735254Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.Type: GrantFiled: March 30, 2021Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Shane Nowell, Steven Michael Kientz, Michael Sheperek, Mustafa N Kaynak, Kishore Kumar Muchherla, Larry J Koudele, Bruce A Liikanen
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Patent number: 11733929Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.Type: GrantFiled: August 15, 2022Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Steve Kientz
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Patent number: 11727994Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.Type: GrantFiled: December 6, 2021Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Larry J. Koudele
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Patent number: 11721399Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.Type: GrantFiled: October 18, 2021Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Steve Kientz