Abstract: Pattern recognition based on associative pattern memory (APM) and properties of cycles generated by finite cellular automata. APM addresses (e.g., positions in a two dimensional array) represent states. Cycles are repeating sequences of addresses. Each state is mapped to a “randomly” selected region within the input pattern. Each feature extracted from this region determines one of many next states. All next states (one for each feature type) and all sampled regions are assigned to each state randomly upon APM initialization. The process progresses from state to state, sampling regions of the pattern until the state-transition sequence repeats (generates a cycle). Each feature pattern is represented by one cycle, however different cycles can be derived from one pattern depending on the initial state. Some embodiments use a refractory period assuring a minimum cycle length, making it likely that any given pattern yields only one cycle independent of the initial state.

Abstract: Pattern recognition based on associative pattern memory (APM) and properties of cycles generated by finite cellular automata. APM addresses (e.g., positions in a two dimensional array) represent states. Cycles are repeating sequences of addresses. Each state is mapped to a “randomly” selected region within the input pattern. Each feature extracted from this region determines one of many next states. All next states (one for each feature type) and all sampled regions are assigned to each state randomly upon APM initialization. The process progresses from state to state, sampling regions of the pattern until the state-transition sequence repeats (generates a cycle). Each feature pattern is represented by one cycle, however different cycles can be derived from one pattern depending on the initial state. Some embodiments use a refractory period assuring a minimum cycle length, making it likely that any given pattern yields only one cycle independent of the initial state.

Abstract: Pattern recognition based on associative pattern memory (APM) and properties of cycles generated by finite cellular automata. APM addresses (e.g., positions in a two dimensional array) represent states. Cycles are repeating sequences of addresses. Each state is mapped to a “randomly” selected region within the input pattern. Each feature extracted from this region determines one of many next states. All next states (one for each feature type) and all sampled regions are assigned to each state randomly upon APM initialization. The process progresses from state to state, sampling regions of the pattern until the state-transition sequence repeats (generates a cycle). Each feature pattern is represented by one cycle, however different cycles can be derived from one pattern depending on the initial state. Some embodiments use a refractory period assuring a minimum cycle length, making it likely that any given pattern yields only one cycle independent of the initial state.

Abstract: A system allows a user to create and process data forms using familiar word processing and data base computer programs. The invention allows for form creation without interfacing with custom form software, but instead uses a known word processing program interface. The user, therefore, can be more efficient and has the tools provided with the word processing program. The present system can extract data from completed forms. This is performed through a scanning operation and a template. The extracted data can then be placed in a commercially available database program for processing.

Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides a sequence of addresses (or "address stream") to the image buffer and to a response memory. The next address provided by the address sequencer is based upon the current address and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats and address, the address stream is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated since the address sequencer always produces the same next address based upon the same current address and the same sample value stored at that current address.

Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides a sequence of addresses (or "address stream") to the image buffer and to a response memory. The next address provided by the address sequencer is based upon the current address and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats and address, the address stream is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated since the address sequencer always produces the same next address based upon the same current address and the same sample value stored at that current address.

Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. During a training mode, a pattern to be recognized is supplied to the image buffer and a training code representing a desired response is written into the response memory at selected locations that correspond to addresses in the address loop being generated.

Abstract: An address sequencer produces an address stream which includes a plurality of interleaved sequences of addresses. Each sequence is a function of input data which is received when an input pattern is sampled by that sequence, so that a repetitive address loop is generated which characterizes the pattern. The address sequencer includes a shift register with a programmable feedback circuit which provides a feedback bit to the first stage of the shift register based upon bits from selected stages of the shift register. During each operating cycle of the address sequencer, a counter provides a sequence identification number which identifies a particular sequence. A stored address selected by the sequence identification number is provided as the present address for that sequence (and the output of the address sequencer). In addition, the shift register is loaded with a multibit word derived from that stored address.

Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides a sequence of addresses (or "address stream") to the image buffer and to a response memory. The next address provided by the address sequencer is based upon the current address and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address, the address stream is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated, since the address sequencer always produces the same next address based upon the same current address and the same sample value stored at that current address.

Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated, since the address sequencer always produces the same next address for that sequence based upon the same current address and the same sample value stored at that current address.

Abstract: Pattern recognition based on associative pattern memory (APM) and properties of cycles generated by finite cellular automata. APM addresses (e.g., positions in a two dimensional array) represent states. Cycles are repeating sequences of addresses. Each state is mapped to a “randomly” selected region within the input pattern. Each feature extracted from this region determines one of many next states. All next states (one for each feature type) and all sampled regions are assigned to each state randomly upon APM initialization. The process progresses from state to state, sampling regions of the pattern until the state-transition sequence repeats (generates a cycle). Each feature pattern is represented by one cycle, however different cycles can be derived from one pattern depending on the initial state. Some embodiments use a refractory period assuring a minimum cycle length, making it likely that any given pattern yields only one cycle independent of the initial state.