Abstract: A printed circuit board assembly (PCBA) may include a printed circuit board (PCB), a socket mechanically and electrically coupled to the PCB, and an integrated circuit package electrically coupled to the socket. The PCBA also may include a thermal cover comprising a thermally conductive material and a thermal strap thermally coupled to the thermal cover. The thermal cover may be thermally coupled to the integrated circuit package and mechanically urge the integrated circuit package in contact with the socket, and the thermal strap may include a thermally conductive material.

Abstract: A printed circuit board assembly (PCBA) may include a printed circuit board (PCB), a socket mechanically and electrically coupled to the PCB, and an integrated circuit package electrically coupled to the socket. The PCBA also may include a thermal cover comprising a thermally conductive material and a thermal strap thermally coupled to the thermal cover. The thermal cover may be thermally coupled to the integrated circuit package and mechanically urge the integrated circuit package in contact with the socket, and the thermal strap may include a thermally conductive material.

Abstract: A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.

Abstract: A cable interface device is provided for physically and electronically connecting two devices. The cable interface device comprises a first pin pickup assembly electrically connectable to a first multi-pin connector of a first electronic device having a first pin geometry. The device also includes a hardware specific signal routing adapter connected electronically and physically in series with the pin pickup assembly and a second pin pickup assembly electrically connectable to a second pin connector of a second electronic device having a second pin geometry, the second pin geometry being electronically and mechanically different from the first pin geometry.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

Abstract: The illustrative embodiment of the present invention is a system and a method for the detection and limited identification of biological agents. The system is small, light weight, requires little power to operate and uses few consumables. The system can be configured for use in either stationary or mobile applications. The system incorporates elements that enable it to obtain an air sample, extract +particulates from the air sample onto a stationary-phase collection media, exposes the particulates to electromagnetic radiation, and monitor for fluorescent emissions. To the extent that fluorescent emissions are detected and exceed a predetermined value, an alarm is triggered. In some embodiments, in addition to performing real-time analyses on the extracted particulates, the collection media is removed from the system and the sample is subjected to more detailed analysis via additional equipment (e.g., pcr, etc.).

Abstract: The illustrative embodiment of the present invention is a system and a method for the detection and identification of biological agents. The system incorporates elements that enable it to obtain an air sample, extract particulates from the air sample onto a stationary-phase collection media, expose the particulates to electromagnetic radiation, and monitor for fluorescent emissions. In some embodiments, particulates are exposed to electromagnetic radiation using a plurality of LEDs, wherein some of the LEDs emit electromagnetic radiation at relatively shorter wavelengths and some other of the LEDs emit electromagnetic radiation at relatively longer wavelengths.

Abstract: The illustrative embodiment of the present invention is a system and a method for the detection and limited identification of biological agents. The system is small, light weight, requires little power to operate and uses few consumables. The system can be configured for use in either stationary or mobile applications. The incorporates elements that enable it to obtain an air sample, extract particulates from the air sample, exposes the particulates to electromagnetic radiation, and monitor for fluorescent emissions. To the extent that fluorescent emissions are detected and exceed a predetermined value, an alarm is triggered.

Abstract: The illustrative embodiment of the present invention is a unmanned aerial vehicle that includes a sensing system for the detection and limited identification of biological agents. The system is small, light weight, requires little power to operate and uses few consumables. The system incorporates elements that enable it to obtain an air sample, extract particulates from the air sample and retain them on a stationary-phase collection media, exposes the particulates to electromagnetic radiation, and monitor the particulates for fluorescent emissions. To the extent that fluorescent emissions are detected and exceed a predetermined value, an alarm is triggered. In some embodiments, in addition to performing real-time analyses on the extracted particulates, the collection media is removed from the system and the sample is subjected to more detailed analysis via additional equipment.

Abstract: The present disclosure concerns an electrical injury protection system for protecting individuals working on or near a power circuit. In one embodiment, the system comprises a controller that is electrically connected to a power circuit and a detector that is carried by a user working. The detector has three or more electrodes mounted on the user's body which detect the electric field induced on the body by the power circuit. The detector is operable to detect the voltage between each pair of electrodes and activate an alarm if the voltage between any electrode pair exceeds a predetermined proximity threshold. If the voltage between an electrode pair exceeds a predetermined electrical-contact threshold, the detector transmits a tripping signal to the controller to activate a tripping mechanism, which de-energizes the power circuit. In certain embodiments, the controller can be used to monitor the de-energized condition of a de-energized circuit.

Abstract: A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

Abstract: A pipeline accelerator includes a memory and a hardwired-pipeline circuit coupled to the memory. The hardwired-pipeline circuit is operable to receive data, load the data into the memory, retrieve the data from the memory, process the retrieved data, and provide the processed data to an external source. In addition or in the alternative, the hardwired-pipeline circuit is operable to receive data, process the received data, load the processed data into the memory, retrieve the processed data from the memory, and provide the retrieved processed data to an external source. Where the pipeline accelerator is coupled to a processor as part of a peer-vector machine, the memory facilitates the transfer of data—whether unidirectional or bidirectional—between the hardwired-pipeline circuit(s) and an application that the processor executes.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations.

Abstract: A modular duplex media handling system is installable for use with a print recording system having a simplex media handling system. During first side printing a media sheet is fed along a first media path in the simplex system from feed rollers to metering rollers and into a print zone. After first side printing and prior to releasing the media sheet, the metering rollers feed the media sheet back along the first media path to the feed rollers. The feed rollers in turn feed the media sheet completely into the duplex module where the media moves along a loop path (in effect flipping the media sheet). The media sheet then is fed back to the feed rollers and along the first media path for second side printing. A humidity sensor in the duplex module signals to the print recording system whether the duplex handling system is installed.

Abstract: A printhead cartridge and carriage assembly (10) is provided comprising: a carriage (12); a snap-spring (62) for securing a printing cartridge (14) in postion on the carriage; and an interconnect strip (16) for supplying electrical signals to the cartridge, including a force loading spring pad (24) for urging a portion of the interconnect strip against a portion of the cartridge. The cartridge has top (32), bottom (34), sides (36, 38), front (40) and rear (42) surfaces and includes a printhead (44) on the bottom surface, an electrical contact strip (46) on the back surface connected to the printhead, referencing pads (56) on the side surface, and a lip (64) on the back surface for accepting the snap-spring. Referencing surface (60) are provided for receiving the referencing pads on the cartridge. The spring pad urges the interconnect strip against the electrical contact of the cartridge.