Abstract: Systems, apparatuses, and methods for an interface module to interface with an enclosure services processor are described herein. The interface module may include one or more state machines configured to provide an enclosure service operation. Provision of this enclosure service operation may be at least partially unsupervised by a control processor requesting the enclosure service operation. Other embodiments may be described and claimed.

Abstract: Techniques, apparatus, and systems for injecting a memory fault can include obtaining first data and second data different from the first data, generating first error detection information based on the first data, writing the second data to a memory unit using a specified address, and using the first error detection information as error detection information for the second data to create a memory fault condition.

Abstract: An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources, performs a scan of respective vector values of the plurality of IRQs, and selectively outputs a priority based on the scan. An interrupt generation module receives the priority and generates at least one of a fast interrupt and a regular interrupt based on the priority.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: A system and method for an embedded disk controller is provided. The embedded disk controller includes a main processor in communication with a first bus. A second processor communicates with a second bus. An external bus interface controller (“EBC”) located on the embedded disk controller manages a plurality of memory devices external to the system embedded disk controller via an external bus interface and coupled to the first bus and an external bus. Each of the plurality of memory devices has at least one of different timing characteristics and different data widths. The EBC is coupled to the first bus and stores at least one of a segment descriptor register and at least a device range register.

Abstract: A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the bus to one of a plurality of bus agents, and a fairness module imposes a desired degree of fairness to the data transfer resources by mandating data transfer resource access to bus agents whose commands have been subjected to a retry response. The degree of fairness is controllable, in order to appropriately balance the desired throughput and data transfer resource allocation for a particular application.

Abstract: A method of and apparatus for improving the efficiency of a data processing system employing multiple busses operating at multiple data transfer rates. Each of the multiple physical busses has its own characteristics including maximum data transfer rate, parallel word width, etc. Two or more of these physical busses are combined into a single logical bus, wherein the single logical bus has characteristics resulting from the combination of physical busses. These characteristics can include greater parallel word widths, enhanced maximum data transfer rates, etc.

Abstract: A system and method for an embedded disk controller is provided with an external bus interface controller (“EBC”) for managing devices external to the system via an external bus interface, wherein the EBC is coupled to a high performance bus and includes at least a segment descriptor register and at least a device range register. The segment descriptor register allows firmware to program timing characteristics of the devices. The device range register enables the first main processor to access an address space in the devices.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register access to the first or second processor. The hardware mechanism includes a hard semaphore and/or soft semaphore.

Abstract: A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.

Abstract: An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

Abstract: Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is provided for executing each test list, and a run controller is provided for monitoring the execution of each test list. To synchronize the execution of the two or more test lists, the run controller halts the execution of each test list as each test driver assumes a predetermined state. Once all of the test lists are halted, the test lists are synchronized. Once synchronized, selected test drivers are restarted to continue execution of the corresponding test lists in a relatively non-deterministic manner.

Abstract: An apparatus for and method of providing rapid communication between separately clocked system elements. A network interface module is used as the overall system control and communication interface to each of the separate system elements. Each of these system elements is controlled by a different and dedicated programmable micro-engine. A separate register located within and addressable by each of the micro-engines provides the basic data transfer path. Access by a micro-engine to the corresponding register is easily accomplished by firmware. The bit serial scan interface between the network interface module and each of the registers is controlled by the network interface module.

Abstract: A method and apparatus for efficiently download and/or upload critical data elements between a computer's memory to/from a data save disk system, when a failure of a primary power source is detected. This is accomplished by coupling the data save disk system directly to the memory module such that the data elements in the memory module may be downloaded directly to the data save disk system without any intervention by a host computer. This configuration may have a number of advantages. First, the speed at which the data elements may be downloaded from the memory module to the data save disk system may be enhanced due to the direct coupling therebetween. Second, significant power savings may be realized because only the memory module and the data save disk system need to be powered by a secondary power source to effect the download operation.