Patents by Inventor Larry P. Henson
Larry P. Henson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030088611Abstract: The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.Type: ApplicationFiled: May 7, 2002Publication date: May 8, 2003Applicant: MTI Technology CorporationInventors: Kumar Gajjar, Larry P. Henson
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Patent number: 6385674Abstract: The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.Type: GrantFiled: September 20, 1999Date of Patent: May 7, 2002Assignee: MTI Technology CorporationInventors: Kumar Gajjar, Larry P. Henson
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Patent number: 5956524Abstract: The present invention is directed to a novel apparatus for "on-the-fly" data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status.Type: GrantFiled: July 10, 1997Date of Patent: September 21, 1999Assignee: Micro Technology Inc.Inventors: Kumar Gajjar, Larry P. Henson
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Patent number: 5715406Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.Type: GrantFiled: November 9, 1994Date of Patent: February 3, 1998Assignee: EMC CorporationInventors: Larry P. Henson, Kumar Gajjar, Thomas E. Idleman
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Patent number: 5651110Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.Type: GrantFiled: April 12, 1995Date of Patent: July 22, 1997Assignee: Micro Technology Corp.Inventors: David T. Powers, David H. Jaffe, Larry P. Henson, Hoke S. Johnson, III, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5414818Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.Type: GrantFiled: April 6, 1990Date of Patent: May 9, 1995Assignee: MTI Technology CorporationInventors: Larry P. Henson, Kumar Gajjar, Thomas E. Idleman
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Patent number: 5285451Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.Type: GrantFiled: July 15, 1992Date of Patent: February 8, 1994Assignee: Micro Technology, Inc.Inventors: Larry P. Henson, Kumar Gajjar, David T. Powers, Thomas E. Idleman
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Patent number: 5274645Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.Type: GrantFiled: April 23, 1992Date of Patent: December 28, 1993Assignee: Micro Technology, Inc.Inventors: Thomas E. Idleman, Robert S. Koontz, David T. Powers, David H. Jaffe, Larry P. Henson, Joseph S. Glider, Kumar Gajjar
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Patent number: 5212785Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.Type: GrantFiled: April 6, 1990Date of Patent: May 18, 1993Assignee: Micro Technology, Inc.Inventors: David T. Powers, David H. Jaffe, Larry P. Henson, Hoke S. Johnson III, Joseph S. Glider, Thomas E. Idleman
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Patent number: 5140592Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.Type: GrantFiled: October 22, 1990Date of Patent: August 18, 1992Assignee: SF2 CorporationInventors: Thomas E. Idleman, Robert S. Koontz, David T. Powers, David H. Jaffe, Larry P. Henson, Joseph S. Glider, Kumar Gajjar
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Patent number: 5134619Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.Type: GrantFiled: April 6, 1990Date of Patent: July 28, 1992Assignee: SF2 CorporationInventors: Larry P. Henson, Kumar Gajjar, David T. Powers, Thomas E. Idleman