Abstract: An apparatus for generating an activity article, the apparatus includes at least a processor and a memory, wherein the memory contains instructions configuring the at least a processor to receive activity data from an activity data source, determine an activity classification as a function of the activity data, select a plurality of tokens as a function of the activity classification, and generate an activity article as a function of the plurality of tokens, wherein the activity article containing contains an activity article link.

Abstract: A high-power pulsed surface processing system includes insulated-gate bipolar transistors (IGBT) to replicate desirable pulse structures with high precision, at low cost, and with high reliability within a single system. The pulsed surface processing system includes a power supply, an anode and a cathode, a dual gate driver supplying power to one or more IGBT gates, and one or more capacitor banks. Pulse formation software controls the timing and duration of electrical pulses to the electrodes. A freewheeling diode protects the system from an abrupt reduction of current in the circuit. The high-power pulsed surface processing system may be used to control versatile and complex pulse structures while with precise control of instantaneous pulse powers, pulse timing, and process control. The inclusion of dual gate drivers also offers the ability for multiple pulsers to be created and “slaved” together for a wide variety of custom processes.

Abstract: A high-power pulsed surface processing system includes insulated-gate bipolar transistors (IGBT) to replicate desirable pulse structures with high precision, at low cost, and with high reliability within a single system. The pulsed surface processing system includes a power supply, an anode and a cathode, a dual gate driver supplying power to one or more IGBT gates, and one or more capacitor banks. Pulse formation software controls the timing and duration of electrical pulses to the electrodes. A freewheeling diode protects the system from an abrupt reduction of current in the circuit. The high-power pulsed surface processing system may be used to control versatile and complex pulse structures while with precise control of instantaneous pulse powers, pulse timing, and process control. The inclusion of dual gate drivers also offers the ability for multiple pulsers to be created and “slaved” together for a wide variety of custom processes.

Abstract: In certain situations, it is desirable to mount an engine accessory to a frame member of the vehicle. Such frame member might be a convenient structural element proximate a desired location for the engine accessory. Because the frame member is often hollow, conventional mounting techniques may crush it. A system and method for attaching first and second brackets to the frame member are disclosed. The bracket systems may have piloting, locating, and anti-rotation features to provide secure attachment points. A vehicle accessory is mounted at the distal ends of the first and second brackets.

Abstract: An integrated engine cover and exhaust gas recirculation cooler for an internal combustion engine includes a cover for enclosing a portion of an engine and an EGR cooler having a housing formed as one piece with the cover. The EGR cooler includes at least one cooler section located within the housing and EGR and bypass valves for controlling the flow of exhaust gases either though the cooler or around the cooler.

Abstract: An integrated engine cover and exhaust gas recirculation cooler for an internal combustion engine includes a cover for enclosing a portion of an engine and an EGR cooler having a housing formed as one piece with the cover. The EGR cooler includes at least one cooler section located within the housing and EGR and bypass valves for controlling the flow of exhaust gases either though the cooler or around the cooler.

Abstract: A video data storage system holds MPEG compressed video data on a hard disk drive. A transport decoder receives a bit-stream including the compressed audio and video data formatted as transport packets and that reformats the compressed audio and video data into respective program elementary stream (PES) packets. The system stores the audio and video PES packets onto a disk. The system also includes separate audio and video buffer memories that hold the audio and video PES packets when they are read from the disk drive. An MPEG decoder separately accesses the audio and video data from the respective audio and video buffer memories. The audio buffer memory has an amount of memory sufficient to provide the MPEG decoder with audio data representing ten seconds of decoded audio signal. In one embodiment, when a soft error occurs, the MPEG decoder continues to read and decode data from the audio buffer, but stops reading and decoding data from the video buffer.

Abstract: An apparatus and method for reliably activating explosives includes providing one or more housing sections that define a sealed space. A first explosive element is provided in the sealed space, and a second explosive element has a first portion inside the sealed space, and a second portion outside the sealed space exposed to outside pressure. A gripping mechanism grips a surface of the second explosive element to maintain a position of the second explosive element that is exposed to the outside pressure in an axial direction of the second explosive element.

Abstract: A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which decodes an ATSC encoded image and employs a downconversion process to produce a standard definition video signal. The video decoder includes a frequency-domain filter to reduce the resolution of the ATSC encoded signal. The video decoder downconversion system also includes a formatting section having vertical and horizontal filters, as well as resampling processing, to format the decoded and downconverted video image for a particular display and aspect ratio. The decoder senses the display format of the encoded video signal and changes the processing provided by the decoder to produce a standard definition output signal regardless of the display format of the encoded input signal. The system also includes a format converter which may be programmed to use a plurality of methods to convert the aspect ratio of the input signal for display on a display device having a different aspect ratio.

Abstract: An HDTV down conversion system including apparatus for forming a set of low resolution down-sampled pixel values corresponding to a current frame of a video signal from a set of low resolution pixel values corresponding to a residual image of a current frame of the video signal and from a set of down-sampled low resolution pixel values corresponding to reference frames of the video signal. The apparatus includes a memory for storing the set of down-sampled low resolution pixel values. An up-sampling processor receives from the memory and uses Lagrangian interpolation to convert the set of down-sampled low resolution pixel values corresponding to the reference frame of the video signal into a set of up-sampled low resolution pixel values corresponding to the reference frame of the video signal.

Abstract: A power indicating setter system monitors the power level of a fuze setter coil of a fuze setter system for a gun operable to fire inductively-fuzed shells. The fuze setter system transmits a carrier signal that induces magnetic field power in the fuze setter coil. The strength of the magnetic field power correlates to reliability of the fuze setter system to transmit fuzing data to the shells. The fuze setter coil induces a signal in an adjacent induction element. Circuitry, coupled to the induction element, operates to compare the signal to a calibrated signal produced by the circuitry. The circuitry, by a power indicator, functions to indicate to an operator when the value of the signal is greater than the calibrated value. The power indicator indicates during operation of the gun, thereby informing the operator of the reliability of the fuze setter system to transmit fuzing data to the shells.

Abstract: A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP@HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP@ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP@HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP@HL signal when the decoder is operated in the second mode.

Abstract: A system for expanding a parameter encoding field in a new communications protocol that is compatible with an old protocol. An unused command parameter in an old protocol is used to indicate an expanded parameter encoding field in a new protocol. Parameter encodings from the old protocol are unchanged in the new protocol. A system communicating using the old protocol recognizes all parameters from the old protocol and ignores parameters from the new protocol. A system communicating using the new protocol recognizes parameters from both the old and new protocols.

Abstract: An HDTV down conversion system including an apparatus for forming a low resolution 2:1 down converted video signal from an encoded video signal representing a video image. The encoded video signal is a frequency-domain transformed high resolution video signal with motion prediction. The apparatus includes a receiver for receiving encoded video signals as a plurality of high resolution frequency-domain video coefficient values. A down conversion filter receives and weights the high resolution frequency-domain video coefficient values to form a set of low passed frequency-domain video coefficients. An inverse-transform processor transforms the set of frequency-domain video coefficients into a set of pixel values. An averaging filter transforms selected ones of the pixel values in the set of pixel values into averaged pixel values. A decimating processor deletes selected ones of the set of pixel values to provide the low resolution video signal.

Abstract: An HDTV down conversion system including an apparatus for forming a low resolution 2:1 down converted video signal from an encoded video signal representing a video image. The encoded video signal is a frequency-domain transformed high resolution video signal with motion prediction. The apparatus includes a receiver for receiving encoded video signals as a plurality of high resolution frequency-domain video coefficient values. A down conversion filter receives and weights the high resolution frequency-domain video coefficient values to form a set of low passed frequency-domain video coefficients. An inverse-transform processor transforms the set of frequency-domain video coefficients into a set of pixel values. An averaging filter transforms selected ones of the pixel values in the set of pixel values into averaged pixel values. A decimating processor deletes selected ones of the set of pixel values to provide the low resolution video signal.

Abstract: An anchoring system and method for temporary structures is disclosed. The system comprises: At least a first stake having a shaft with a lower end for insertion into the ground, and an upper end including a loop; at least a second stake having a shaft with a lower end for insertion into the ground, and an upper end including at least one hook. When the lower ends of the at least first and second stakes are inserted into the ground, the lower ends of the stakes are angled away from each other, the shaft of the second stake is received through the loop of the first stake, and a portion of the shaft of the first stake is received within the at least one hook, whereby the at least first and second stakes are in a mutually interlocked condition which prevents the at least first and second stakes from being independently extracted from the ground.

Abstract: An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and off processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform.

Abstract: An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and odd processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform. The 1-D IDCT processors each include input section circuits which each receive four-bits of 12-bit or 16-bit input values and provides one bit of each of four input values in a four clock cycle time period.

Abstract: An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and odd processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform. The 1-D IDCT processors each include input section circuits which each receive four-bits of 12-bit or 16-bit input values and provides one bit of each of four input values in a four clock cycle time period.